Zarlink Semiconductor Inc.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

Features

· Single chip mixer/oscillator PLL combination for

multi band tuner for DTT applications

· Each mixer oscillator band optimized for wide

dynamic range

· RF input stages allow for either single-ended or

differential drive

· PLL frequency synthesizer designed for low

phase noise performance

· Broadband output level detect with onset adjust

· PLL frequency synthesizer compatible with

standard digital terrestrial offsets

· Four integrated switching ports

· I

C fast mode compliant

· ESD protection (Normal ESD handling

procedures should be observed)

Applications

· Terrestrial digital receiver systems

· Terrestrial analogue receiver systems

· Cable receiver systems

· Data communications systems

Description

The SL2610 is a mixer oscillator intended primarily
for application in all band tuners, where it performs
image reject downconversion of the RF channel to a
standard 36 MHz or 44 MHz IF.

Each band consists of a low noise preamplifier/mixer
and local oscillator with an external varactor tuned
tank. The band outputs share a common low
impedance SAWF driver stage.

Frequency selection is controlled by the on-board I

bus frequency synthesizer. This block also controls
four general purpose switching ports for selecting the
prefilter/AGC stages.

October 2004

Ordering Information

SL2610/IG/LH1Q 40 Pin MLP Tape & Reel, Bake & Drypack
SL2610/IG/LH1N 40 Pin MLP Trays, Bake & Drypack

SL2610/IG/LH2Q 40 Pin MLP Tape & Reel, Bake & Drypack*

SL2610/IG/LH2N 40 Pin MLP Trays, Bake & Drypack*

*Leadfree

-40

C to +85

SL2610

Wide Dynamic Range Image Reject MOPLL

Data Sheet

Figure 1 - SL2610 Block Diagram

CONVOP

BAND

MID

BAND

CONVOPB

IFIP
IFIPB
IFOP
IFOPB

AGC BIAS

AGC OUT

BAND

MID

BAND

Interface

Port

Interface

REF

DIVIDER

PORT P0
PORT P1
PORT P2
PORT P3

PROG

DIVIDER

CHARGE

PUMP

DRIVE

XTAL

XTALCAP

SDA SCL ADD

SELECT

SL2610

Data Sheet

Zarlink Semiconductor Inc.

The SL2610 has high intermodulation intercept performance so offering high signal to spurious performance in
the presence of higher amplitude interferers or in the presence of a wide bandwidth composite input signal.

An output broadband level detect circuit is included for control of the tuner front end AGC.

Figure 2 - Pin Allocation Diagram

Quick Reference Data

Characteristics

Units

Frequency range:

LOW band

50-500

MHz

MID band

50-500

MHz

HIGH band

200-900

MHz

Conversion gain *

Noise figure

Typical Image Reject

P1dB input referred, Converter section only

106

dBuV

IP3 input referred, Converter section only

dBm

IP2 input referred, Converter section only

dBm

LO phase noise (free running)

@ 10 kHz offset

-90

dBc/Hz

@ 100 kHz offset

-110

dBc/Hz

PLL phase noise

-158

dBc/Hz

Maximum composite output amplitude

dBm

* Assuming 2 dB shaping filter loss in external IF path.

LH40

PORT P3

VccRF

HI INPUT

PORT P2
PORT P1

MID INPUT

LOL

WOP

LOL

WOP

LOM

I
DOP

VccL

L
O

IIP

LOHI

L
O

IIP

VccL

MID INPUTB

VccRF

LO INPUT

IFOPB

IFOP

AGCBIAS

VCCIF
IFIPB

IFIP
ADD

CONVOP

CONVOPB
VccDIG

VccRF

PUMP

AL CAP

DRIVE

XTAL

SDA

SCL

LOM

I
DOP

HI INPUTB

VEE
(PACKAGE

PADDLE)

Pin 1

SL2610

Data Sheet

Zarlink Semiconductor Inc.

Figure 3 - SL2610 Evaluation Board Schematic

2p2

22nH

8n2H

100pF

5pF

4K7

gnd

SDA

VDD

GND

SCL

CN1

I2C

gnd

4K7

+5V

100nF

47pF

4 M

gnd

47pF

33K

TR1

BCW

gnd

20K

+30V

18K

1n5F

gnd

+5V

82nH

BB640

7pF

36nH

1u5H

6p8F

120nH

BB640

4K7

220nH

82pF

+5V

1nF

5:1

SK4

IF OUT

gnd

1nF

SK1

HI IN

SK2

SK3

gnd

CN2

gnd

+30V

GND

+5V

10nF

gnd

470uF

+30V

100nF

gnd

750R

+5V

10nF

CN3

ADDRESS

gnd

100pF

4K7

gnd

100pF

20R

10R

BB555

10R

10K

PORT

cc R

HIGH IP

HIGH IP B

PORT

I
D IP B

cc R

LO INPUT

INPUT B

Vcc R

AGC OUT

PORT P0

DRIVE

CHARGE PUMP

XTAL

CAP

XTAL

SDA

SCL

cc D

I
G

CONV OP B

CONV OP

ADD

IF INPUT

cc I

AGC BIAS

IF O/P

IF O/P B

VccLO

HII/PB

LOH

HII/P

VccLO

LOM

LOLO

WOP

LOLO

WOP

Vee = Pin 0 = PACKAGE PADDLE

Gnd

SL2610

VR1

10K

+5V

gnd

TP2

TP1

POWER

AGC

ADDRE

S
S

I
2
C Co

n
t
r
o
l

)

RF I

(

OW)

gnd

SL2610

Data Sheet

Zarlink Semiconductor Inc.

1.0 Functional Description

The SL2610 is a multi band RF mixer oscillator with image reject and on-board frequency synthesizer. It is intended
primarily for application in all band terrestrial tuners and requires a minimum external component count. It contains
all elements required for RF downconversion to a standard IF with the exception of external VCO tank circuits.

The pin allocation is contained in Figure 2 and the block diagram in Figure 1.

1.1 Mixer/oscillator section

In normal application the RF input is interfaced to the selected mixer oscillator preamplifier through the tuner
prefilter and AGC stages. The mixer input is arranged such that the signal can be coupled either differentially or
single-ended, and achieves the specified minimum performance in both configurations. Band input impedances
and NF are contained in Figure 11 and Figure 12 respectively. The converter two tone input spectra are contained
in Figure 13 and Figure 14.

The preamplifier output then feeds the mixer stage where the required channel is image reject downconverted to
the IF frequency. The local oscillator frequency for the downconversion is obtained from the on board local
oscillator, which uses an external varactor tuned tank. Typical VCO applications are contained in Figures 8, 9 and
10.

The output of the mixer is then fed to the converter output driver which presents a matched 200

differential load

to an external IF shaping filter.

The output of the shaping filter is then coupled into the IFAMP stage, which provides further gain and offers a 50

output impedance to interface direct with the tuner SAW filter.

The SL2610 contains a broadband level detect circuit whose output can be used to control the tuner AGC. The
target level of the AGC detector is controlled by the voltage applied to the AGCBIAS pin. The characteristic of the
target level is given in Figure 18.

1.2 PLL Frequency Synthesizer

The PLL frequency synthesizer section contains all the elements necessary, with the exception of a frequency
reference and loop filter, to control a varicap tuned local oscillator, so forming a complete PLL frequency
synthesised source. The device allows for operation with a high comparison frequency and is fabricated in high
speed logic, which enables the generation of a loop with good phase noise performance. It can also be operated
with comparison frequencies appropriate for frequency offsets as required in digital terrestrial (DTT) receivers.

The LO signal is multiplexed from the selected oscillator section to an internal preamplifier which provides gain and
reverse isolation from the divider signals. The output of the preamplifier interfaces direct with the 15-bit fully
programmable divider which is of MN+A architecture, where the dual modulus prescaler is 16/17, the A counter is
4-bits and the M counter is 11 bits.

The output of the programmable divider is fed to the phase comparator where it is compared in both phase and
frequency domain with the comparison frequency. This frequency is derived either from the on-board crystal
controlled oscillator or from an external reference source. In both cases the reference frequency is divided down to
the comparison frequency by the reference divider which is programmable into 1 of 29 ratios as detailed in Table 1.

The output of the phase detector feeds a charge pump and loop amplifier section which when used with an external
loop filter integrates the current pulses into the varactor line voltage.

The programmable divider output Fpd, divided by two and the reference divider output Fcomp, can be switched to
port P0 by programming the device into test mode. The test modes are described in Table 5.

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: SL2610LH1N

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: SL2610LH1N