ICROPROCESSOR

ILOG

FEATURES

Z380

ICROPROCESSOR

Static CMOS Design with Low-Power Standby Mode
Option

32-Bit Internal Data Paths and ALU

Operating Frequency
- DC-to-18 MHz at 5V
- DC-to-10 MHz at 3.3V

Enhanced Instruction Set that Maintains Object-Code
Compatibility with Z80

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and Z180

Microprocessors

16-Bit (64K) or 32-Bit (4G) Linear Address Space

16-Bit Data Bus with Dynamic Sizing

RODUCT

PECIFICATION

Two-Clock Cycle Instruction Execution Minimum

Four Banks of On-Chip Register Files

Enhanced Interrupt Capabilities, Including
16-Bit Vector

Undefined Opcode Trap for Z380

Instruction Set

On-Chip I/O Functions:
- Six-Memory Chip Selects with Programmable Waits
- Programmable I/O Waits
- DRAM Refresh Controller

100-Pin QFP Package

GENERAL DESCRIPTION

The Z380

Microprocessor is an integrated high-

performance microprocessor with fast and efficient through-
put and increased memory addressing capabilities. The
Z380

offers a continuing growth path for present Z80-or

Z180-based designs, while maintaining Z80

�

CPU and

Z180

�

MPU object-code compatibility. The Z380

MPU

enhancements include an improved 280 CPU, expanded
4-Gbyte space and flexible bus interface timing.

An enhanced version of the Z80 CPU is key to the Z380
MPU. The basic addressing modes of the Z80 micropro-
cessor have been augmented as follows: Stack Pointer
Relative loads and stores, 16-bit and 24-bit indexed off-
sets, and more flexible Indirect Register addressing, with
all of the addressing modes allowing access to the entire

32-bit address space. Additions made to the instruction
set, include a full complement of 16-bit arithmetic and
logical operations, 16-bit I/O operations, multiply and
divide, plus a complete set of register-to-register loads
and exchanges.

The expanded basic register file of the Z80 MPU micropro-
cessor includes alternate register versions of the IX and IY
registers. There are four sets of this basic Z80 micropro-
cessor register file present in the Z380 MPU, along with the
necessary resources to manage switching between the
different register sets. All of the register-pairs and index
registers in the basic Z80 microprocessor register file are
expanded to 32 bits.

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GENERAL DESCRIPTION

(Continued)

The Z380 MPU expands the basic 64 Kbyte Z80 and Z180
address space to a full 4 Gbyte (32-bit) address space.
This address space is linear and completely accessible to
the user program. The I/O address space is similarly
expanded to a full 4 Gbyte (32-bit) range and 16-bit I/O,
and both simple and block move are added.

Some features that have traditionally been handled by
external peripheral devices have been incorporated in the
design of the Z380 microprocessor. The on-chip peripher-
als reduce system chip count and reduce interconnection
on the external bus. The Z380 MPU contains a refresh
controller for DRAMs that employs a /CAS-before-/RAS
refresh cycle at a programmable rate and burst size.

Six programmable memory-chip selects are available,
along with programmable wait-state generators for each
chip-select address range.

The Z380 MPU provides flexible bus interface timing, with
separate control signals and timing for memory and
I/O. The memory bus control signals provide timing refer-
ences suitable for direct interface to DRAM, static RAM,

EPROM, or ROM. Full control of the memory bus timing is
possible because the /WAIT signal is sampled three times
during a memory transaction, allowing complete user
control of edge-to-edge timing between the reference
signals provided by the Z380 MPU. The I/O bus control
signals allow direct interface to members of the Z80 family
of peripherals, the Z8000 family of peripherals, or the
Z8500 series of peripherals. Figure 1 shows the Z380
block diagram; Figure 2 shows the pin assignments.

Note:

All signals with a preceding front slash, "/", are active Low
e.g., B//W (WORD is active Low); B/W is active Low, only)

Power connections follow conventional descriptions below:

Connection

Circuit

Device

Power

Ground

GND

External Interface Logic

Interrupts

CPU

Refresh

Control

Clock with

Standby

Control

Chip Selects

and Waits

Data (16)

Address (32)

VDD

VSS

/EV

Figure 1. Z380 Functional Block Diagram

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PIN DESCRIPTION

A31-A0

Address Bus (outputs, active High, tri-state). These

non-multiplexed address signals provide a linear memory
address space of four gigabytes. The 32-address signals
are also used to access I/O devices.

/BACK

Bus Acknowledge (output, active Low, tri-state).

This signal, when asserted, indicates that the Z380 MPU
has accepted an external bus request and has tri-stated its
output drivers for the address bus, data bus and the bus
control signals /TREFR, /TREFA, /TREFC, /BHEN, /BLEN,
/MRD, /MWR, /IORQ, /IORD, and /IOWR. Note that the
Z380 MPU cannot provide any DRAM refresh transactions
while it is in the bus acknowledge state.

/BHEN

Byte High Enable (output, active Low, tri-state).

This signal is asserted at the beginning of a memory, or
refresh transaction to indicate that an operation on D15-D8
is requested. For a 16-bit memory transaction, if /MSIZE is
asserted, indicating a byte-wide memory, another memory
transaction is performed to transfer the data on D15-D8,
this time through D15-D8.

/BLEN

Byte Low Enable (output, active Low, tri-state). This

signal is asserted at the beginning of a memory or refresh
transaction to indicate that an operation on D7-D0 is
requested. For a 16-bit memory transaction, if /MSIZE is
asserted, indicating a byte-wide memory, only the data on
D7-D0 will be transferred during this transaction, and
another transaction will be performed to transfer the data
on D15-D8, this time through D7-D0.

/BREQ

Bus Request (input, active Low). When this signal

is asserted, an external bus master is requesting control of
the bus. /BREQ has higher priority than all nonmaskable
and maskable interrupt requests.

BUSCLK

Bus Clock (output, active High, tri-state). This

signal, output by the Z380 MPU, is the reference edge for
the majority of other signals generated by the Z380 MPU.
BUSCLK is a delayed version of the CLK input.

CLKI

Clock/Crystal (input, active High). An externally

generated direct clock can be input at this pin and the
Z380 MPU would operate at the CLKI frequency. Alterna-
tively, a crystal up to 20 MHz can be connected across
CLKI and CLKO, and the Z380 MPU would operate at half
of the crystal frequency. The two clocking options are
controlled by the CLKsel input.

CLKO

Crystal (output, active High). Crystal oscillator

connection. This pin should be left open if an externally
generated direct clock is input at the CLKI pin.

CLKsel

Clock Option Select (input, active High). This

input should be connected to V

to select the direct clock

option and should be connected to V

for the crystal

option.

D15-D0

Data Bus (input/outputs, active High, tri-state).

This bi-directional 16-bit data bus is used for data transfer
between the Z380 MPU and memory or I/O devices. Note
that for a memory word transfer, the even-addressed
(A0 = 0) byte is generally transferred on D15-D8, and the
odd-addressed (A0 = 1) byte on D7-D0 (see the /MSIZE
pin description).

/EV

Evaluation Mode (input, active Low). This input should

be left unconnected for normal operation. When it is driven
to logic 0, the Z380 MPU conditions itself in the reset mode
and tri-states all of its output pin drivers.

/HALT

Halt Status (output, active Low, tri-state). If the Z380

MPU standby mode option is not selected, a Sleep instruc-
tion is executed no different than a Halt instruction, and the
one HALT signal goes active to indicate the CPU's HALT
state. If the standby mode option is selected, this signal
goes active only at the Halt instruction execution.

/STNBY

Standby Status (output, active Low, tri-state). If

the Z380 MPU standby mode is selected, executing a
sleep instruction stops clocking within the Z380 MPU and
at BUSCLK and IOCLK after which this signal is asserted.
The Z380 MPU is then in the low power standby mode, with
all operations suspended.

/INT3-0

Interrupt Requests (inputs, active Low). These

signals are four asynchronous maskable interrupt inputs.

IOCLK

I/O Clock (output, active High, tri-state). This signal

is a program controlled divided-down version of BUSCLK.
The division factor can be two, four, six or eight with I/O
transactions and interrupt-acknowledge transactions oc-
curring relative to IOCLK.

/INTAK

Interrupt Acknowledge Status (output, active Low,

tri-state). This signal is used to distinguish between I/O and
interrupt acknowledge transactions. This signal is High
during I/O read and I/O write transactions and Low during
interrupt acknowledge transactions.

/IORQ

Input/Output Request (output, active Low, tri-state).

This signal is active during all I/O read and write transac-
tions and interrupt acknowledge transactions.

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/RESET

Reset (input, active Low). This input must be

active for a minimum of five BUSCLK periods to initialize
the Z380 MPU. The effect of /RESET is described in detail
in the Reset section.

/TREFA

Timing Reference A (output, active Low, tri-state).

This timing reference signal goes Low at the end of T2 and
returns High at the end of T4 during a memory read,
memory write or refresh transaction. It can be used to
control the address multiplexer for a DRAM interface or as
the /RAS signal at higher processor clock rates.

/TREFC

Timing Reference C (output, active Low, tri-state).

This timing reference signal goes Low at the end of T3 and
returns High at the end of T4 during a memory read,
memory write or refresh transaction. It can be used as the
/CAS signal for DRAM accesses.

/TREFR

Timing Reference R (output, active Low, tri-state).

This timing reference signal goes Low at the end of T1 and
returns High at the end of T4 during a memory read,
memory write or refresh transaction. It can be used as the
/RAS signal for DRAM accesses.

/UMCS

Upper Memory Chip Select (output, active Low, tri-

state). This signal is activated during a memory read,
memory write, or optionally a refresh transaction when
accessing the highest portion of the linear address space
within the first 16 Mbytes, but only if this chip select
function is enabled.

Power Supply. These eight pins carry power to the

device. They must be tied to the same voltage externally.

Ground. These eight pins are the ground references for

the device. They must be tied to the same voltage exter-
nally.

/WAIT

Wait (input, active Low). This input is sampled by

BUSCLK or IOCLK, as appropriate, to insert Wait states
into the current bus transaction.

The conditioning and characteristics of the Z380 MPU pins
under various operation modes are defined in Table 1.

/M1

Machine Cycle One (output, active Low, tri-state). This

signal is active during interrupt acknowledge and RETI
transactions.

/IORD

Input, Output Read Strobe (output, active Low, tri-

state). This signal is used strobe data from the peripherals
during I/O read transactions. In addition, /IORD is active
during the special RETI transaction and the I/O heartbeat
cycle in the Z80 protocol case.

/IOWR

Input/Output Write Strobe (output, active Low, tri-

state). This signal is used to strobe data into the peripher-
als during I/O write transactions.

/LMCS

Low Memory Chip Select (output, active Low, tri-

state). This signal is activated during a memory read or
memory write transaction when accessing the lower por-
tion of the linear address space within the first 16 Mbytes,
but only if this chip select function is enabled.

/MCS3-/MCS0

Mid-range Memory Chip Selects (output,

active Low, tri-state). These signals are individually active
during memory read or write transactions when accessing
the mid-range portions of the linear address space within the
first 16 Mbytes. These signals can be individually enabled
or disabled.

/MRD

Memory Read (output, active Low, tri-state). This

signal indicates that the addressed memory location should
place its data on the data bus as specified by the /BHEN
and /BLEN control signals. /MRD is active from the end of
T1 until the end of T4 during memory read transactions.

/MSIZE

Memory Size (input, active Low). This input, from

the addressed memory location, indicates if it is word size
(logic High) or byte size (logic Low). In the latter case, the
addressed memory should be connected to the D15-D8
portion of the data bus, and an additional memory transac-
tion will automatically be generated to complete a word
size data transfer.

/MWR

Memory Write (output, active Low, tri-state). This

signal indicates that the addressed memory location should
store the data on the data bus, as specified by the /BHEN
and /BLEN control signals. /MWR is active from the end of
T2 until the end of T4 during memory write transactions.

/NMI

Nonmaskable Interrupt (input, falling edge-triggered).

This input has higher priority than the maskable interrupt
inputs /INT3-INT0.

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Электронный компонент: Z380