Z5380 SCSI

ILOG

PS97SCC0100

RODUCT

PECIFICATION

FEATURES

Pin Compatible with the Industry Standard 5380

40-Pin DIP or 44-Pin PLCC Package Styles

Low-Power CMOS

Asynchronous Interface (Supports 1.5 MB/s)

Direct SCSI Bus Interface with On-Board 48 mA Drivers

Supports Target and Initiator Roles

Arbitration Support

DMA or Programmed I/O Data Transfers

Supports Normal or Block Mode DMA

Memory or I/O Mapped CPU Interface

The Z5380 SCSI (Small Computer System Interface) con-
troller is designed to implement the SCSI protocol as
defined by the ANSI X3.131-1986 standard, and is fully
compatible with the industry standard 5380. It is capable
of operating both as a Target and as an Initiator. Special
high-current open-drain outputs enable the Z5380 to di-
rectly interface to, and drive, the SCSI bus. The Z5380 has
the necessary interface hook-ups which allows the system
CPU to communicate with it like any other peripheral
device. The CPU can read from, or write to, the SCSI
registers which are addressed as standard or memory-
mapped I/Os (Figure 1).

The Z5380 increases the system performance by minimiz-
ing the CPU intervention in DMA operations which the SCSI
controls. The CPU is interrupted by the SCSI when it

detects a bus condition that requires attention. It also
supports arbitration and reselection. The Z5380 has the
proper hand-shake signals to support normal and block
mode DMA operations with most DMA controllers avail-
able (Figure 2).

Notes:

All Signals with a preceding front slash, "/", are active Low, e.g.,
B//W (WORD is active Low); /B/W (BYTE is active Low, only).

Power connections follow conventional descriptions below:

Connection

Circuit

Device

Power

Ground

GND

GENERAL DESCRIPTION

Z5380 SCSI

MALL

OMPUTER

YSTEM

NTERFACE

(SCSI)

PS009101-0201

Z5380 SCSI

ILOG

PS97SCC0100

/DB7

/DB6

/DB5

/BSY

/ACK

/ATN

/RST

I//O

C//D

/MSG

/REQ

VDD

/IOW

/RESET

/EOP

/DACK

READY

/IOR

IRQ

DRQ

/CS

/DB4

/DB3

/DB2

/DB1

/DB0

/DBP

GND

/SEL

Z5380

PIN DESCRIPTION

Microprocessor Bus

Figure 3 shows the pins and their respective functions for
both the DIP and PLCC.

A2-A0

Address Lines (Input). Address lines are used with

/CS, /IOR, or /IOW to address all internal registers.

/CS

Chip Select (Input, Active Low). This signal, in con-

junction with /IOR or /IOW, enables the internal register
selected by A2-A0, to be read from or written to.

/DACK

DMA Acknowledge (Input, Active Low). /DACK

resets DRQ and selects the data register for input or output
data transfers. /DACK is used by DMA controller instead of
/CS.

DRQ

DMA Request (Output, Active High). DRQ indicates

that the data register is ready to be read or written. DRQ is
asserted only if DMA mode is set in the Command Regis-
ter. DRQ is cleared by /DACK.

/DB3

/DB2

/DB1

44 43 42 41 40

/DB4

/DB5

/DB6

/DB7

N/C

/DB0

/DBP

GND

/SEL

/BSY

/ACK

/ATN

VDD

N/C

/IOW

/RESET

/EOP

/DACK

/RST

I//O

C//D

/MSG

/REQ

N/C

/CS

DRQ

IRQ

/IOR

RDY

18 19 20 21 22 23 24 25 26 27 28

Z5380

D7-D0

Data Lines (Bi-directional, three-state, Active High).

Bi-directional microprocessor data bus lines. D0 is the
Least Significant Bit of the bus. Data bus lines carry data
and commands to and from the SCSI.

/EOP

End of Process (Input, Active Low). /EOP is used to

terminate a DMA transfer. If asserted during a DMA cycle,
the current byte will be transferred, but no additional bytes
will be requested.

/IOR

I/O Read (Input, Active Low). /IOR is used in conjunc-

tion with /CS and A2-A0 to read an internal register. It also
selects the Input Data Register when used with /DACK.

/IOW

I/O Write (Input, Active Low). /IOW is used in conjunc-

tion with /CS and A2-A0 to write an internal register. It also
selects the Output Data Register when used with /DACK.

Figure 3a. 40-Pin DIP Pin Configuration

Figure 3b. 44-Pin PLCC Pin Configuration

PS009101-0201

Z5380 SCSI

PS97SCC0100

ILOG

/DB7-/DB0, /DBP

Data Bus Bits, Data Bus Parity Bit (Bi-

directional, Open-drain). These eight data bits (/DB7-/
DB0), plus a parity bit (/DBP) form the data bus. /DB7 is the
most significant bit (MSB) and has the highest priority
during the Arbitration phase. Data parity is odd. Parity is
always generated and optionally checked. Parity is not
valid during Arbitration.

I//O

Input/Output (Bi-directional, Open-drain). I/O is a

signal driven by a Target which controls the direction of
data movement on the SCSI bus. True indicates input to the
Initiator. This signal is also used to distinguish between
Selection and Reselection phases.

/MSG

Message (Bi-directional, Open-drain, Active Low).

This signal is driven by the Target during the Message
phase. This signal is received by the Initiator.

/REQ

Request (Bi-directional, Open-drain, Active Low).

Driven by the Target and received by the Initiator, this
signal indicates a request for a /REQ//ACK data-transfer
handshake.

/RST

SCSI Bus Reset (Bi-directional, Open-drain, Active

Low). This signal indicates a SCSI bus Reset condition.

/SEL

Select (Bi-directional, Open-drain, Active Low). This

signal is used by an Initiator to select a Target, or by a
Target to reselect an Initiator.

PIN DESCRIPTION

(Continued)

IRQ

Interrupt Request (Output, Active High). IRQ alerts a

microprocessor of an error condition or an event comple-
tion.

READY

Ready (Output, Active High). Ready is used to

control the speed of Block Mode DMA transfers. This
signal goes active to indicate the chip is ready to send/
receive data and remains Low after a transfer until the last
byte is sent or until the DMA Mode bit is reset.

/RESET

Reset (Input, Active Low). /RESET clears all reg-

isters. It has no effect upon the SCSI /RST signal.

SCSI Bus

The following signals are all bi-directional, active Low,
open-drain, with 48 mA sink capability. All pins interface
directly with the SCSI bus.

/ACK

Acknowledge (Bi-directional, Open-drain, Active

Low). Driven by an Initiator, /ACK indicates an acknowl-
edgment for a /REQ//ACK data-transfer handshake. In the
Target role, /ACK is received as a response to the /REQ
signal.

/ATN

Attention (Bi-directional, Open-drain, Active Low).

Driven by an Initiator, received by the Target, /ATN indi-
cates an Attention condition.

/BSY

Busy (Bi-directional, Open-drain, Active Low). This

signal indicates that the SCSI bus is being used and can
be driven by both the Initiator and the Target device.

C//D

Control/Data (Bi-directional, Open-drain). Driven by

the Target and received by the Initiator, C//D indicates
whether Control or Data information is on the Data Bus.
True indicates Control.

FUNCTIONAL DESCRIPTION

implement all or any of the SCSI protocol in software. These
registers are read (written) by activating /CS with an
address on A2-A0 and then issuing an /IOR (/IOW) pulse.
This section describes the operation of the internal regis-
ters (Table 1).

The Z5380 Small Computer System Interface (SCSI) has a
set of eight registers that are controlled by the CPU. By
reading and writing the appropriate registers, the CPU
may initiate any SCSI Bus activity or may sample and
assert any signal on the SCSI Bus. This allows the user to

PS009101-0201

Z5380 SCSI

ILOG

PS97SCC0100

Table 1. Register Summary

Address

R/W

Register Name

Current SCSI Data

Output Data

R/W

Initiator Command

R/W

Mode

R/W

Target Command

Current SCSI Bus Status

Select Enable

Bus and Status

Start DMA Send

Input Data

Start DMA Target Receive

Reset Parity/Interrupt

Start DMA Initiator Receive

Data Registers

The data registers are used to transfer SCSI commands,
data, status, and message bytes between the micropro-
cessor Data Bus and the SCSI Bus. The Z5380 does not
interpret any information that passes through the data
registers. The data registers consist of the transparent
Current SCSI Data Register, the Output Data Register, and
the Input Data Register.

Current SCSI Data Register.

Address 0 (Read Only). The

Current SCSI Data Register (Figure 4) is a read-only
register which allows the microprocessor to read the active
SCSI Data Bus. This is accomplished by activating /CS
with an address on A2-A0 of 000 and issuing an /IOR pulse.
If parity checking is enabled, the SCSI Bus parity is
checked at the beginning of the read cycle. This register
is used during a programmed I/O data read or during
Arbitration to check for higher priority arbitrating devices.
Parity is not guaranteed valid during Arbitration.

Output Data Register.

Address 0 (Write Only). The Output

Data Register (Figure 5) is a write-only register that is used
to send data to the SCSI Bus. This is accomplished by
either using a normal CPU write, or under DMA control, by
using /IOW and /DACK. This register also asserts the
proper ID bits on the SCSI Bus during the Arbitration and
Selection phases.

/DB0

/DB1

/DB2

/DB3

/DB4

/DB5

/DB6

/DB7

Address: 0

(Read Only)

D7 D6 D5 D4 D3 D2 D1 D0

/DB0

/DB1

/DB2

/DB3

/DB4

/DB5

/DB6

/DB7

D7 D6 D5 D4 D3 D2 D1 D0

Address: 0

(Write Only)

Figure 5. Output Data Register

Initiator Command Register.

Address 1 (Read/Write).

The Initiator Command Register (Figures 6 and 7) are read
and write registers which assert certain SCSI Bus signals,
monitors those signals, and monitors the progress of bus
arbitration. Many of these bits are significant only when
being used as an Initiator; however, most can be used
during Target role operation.

Figure 4. Current SCSI Data Register

PS009101-0201

Электронный компонент: Z5380SCSI