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LOG.
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Z8018x
Family MPU
User Manual
UM005001-ZMP0400
Z8018x
Family MPU User Manual
UM005001-ZMP0400
This publication is subject to replacement by a later edition. To determine whether a later edition
exists, or to request copies of publications, contact
ZiLOG Worldwide Headquarters
910 E. Hamilton Avenue
Campbell, CA 95008
Telephone: 408.558.8500
Fax: 408.558.8300
www.ZiLOG.com
Windows is a registered trademark of Microsoft Corporation.
Document Disclaimer
2000 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices,
applications, or technology described is intended to suggest possible uses and may be superseded. ZiLOG,
INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF
THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZiLOG
ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT
RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY
DESCRIBED HEREIN OR OTHERWISE. Except with the express written approval ZiLOG, use of
information, devices, or technology as critical components of life support systems is not authorized. No
licenses or other rights are conveyed, implicitly or otherwise, by this document under any intellectual property
rights.
Z8018x Family
MPU User Manual
UM005001-ZMP0400
iii
MANUAL OBJECTIVES
This user manual describes the features of the Z8018x Family MPUs.This
manual provides basic programming information for the Z80180/Z8S180/
Z8L180. These cores and base perippheral sets are used in a large family
of ZiLOG products. Below is a list of ZiLOG products that use this class
of processor, along with the associated processor family.This document is
also the core user manual for the following products:
Intended Audience
This manual is written for those who program the Z8018x Family.
Manual Organization
The Z8018x Family User Manual is divided into five sections, seven
appendices, and an index.
Part
Family
Z80180
Z80180
Z8S180
Z8S180
Z8L180
Z8L180
Z80181
Z80180
Z80182
Z80180, Z8S180*
Z80S183
Z8S180
Z80185/195
Z8S180
Z80189
Z8S180
* Part number-dependant
Z8018x Family
MPU User Manual
UM005001-ZMP0400
iv
Sections
Z8018X MPU Operation
Presents features, a general description, pins descriptions, block
diagrams, registers, and details of operating modes for the Z8018x MPUs.
Software Architecture
Provides instruction sets and CPU registers for the Z8018x MPUs.
DC Characteristics
Presents the DC parameters and absolute maximum ratings for the
Z8X180 MPUs.
AC Characteristics
Presents the AC parameters for the Z8018x MPUs.
Timing Diagrams
Contains timing diagrams and standard test conditions for the Z8018x
MPUs.
Appendices
The appendixes in this manual provide additional information applicable
to the Z8018x family of ZiLOG MPUs:
Instruction set
Instruction summary table
Op Code map
Bus Control signal conditions in each machine cycle and interrupt
conditions
Operating mode summary
Status signals
I/O registers and ordering information
Z8018x Family
MPU User Manual
UM005001-ZMP0400
v
Table of Contents
Z80180, Z8S180, Z8L180 MPU Operation . . . . . . . . . . . . . . . . . . . .1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
CPU Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Wait State Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
HALT and Low Power Operation Modes
(Z80180-Class Processors Only) . . . . . . . . . . . . . . . . . . . . . . . .31
Low Power Modes
(Z8S180/Z8L180 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Add-On Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
STANDBY Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
STANDBY Mode Exit wiht BUS REQUEST . . . . . . . . . . . . . . . . .38
STANDBY Mode EXit with External Interrupts . . . . . . . . . . . . . . .39
IDLE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
STANDBY-QUICK RECOVERY Mode . . . . . . . . . . . . . . . . . . . .41
Internal I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
MMU Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Interrupt Acknowledge Cycle Timings . . . . . . . . . . . . . . . . . . . . . .82
Interrupt Sources During RESET . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Dynamic RAM Refresh Control . . . . . . . . . . . . . . . . . . . . . . . . . . .86
DMA Controller (DMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Asynchronous Serial Communication Interface (ASCI) . . . . . . . .115