PS014003-0603

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Z80180

Microprocessor Unit

PS014003-0603

Table of Contents

iii

Table of Contents

Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Multiplexed Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . 15

Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Standard Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . 30

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
ASCI Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
ASCI Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
ASCI Transmit Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Channel 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Channel 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
ASCI Receive Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Channel 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Z80180
Microprocessor Unit

PS014002-0403

Table of Contents

Channel 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

ASCI Channel Control Register A . . . . . . . . . . . . . . . . . . . . . . . 57
ASCI CHANNEL CONTROL REGISTER B . . . . . . . . . . . . . . . . 60
ASCI Status Register 0, 1 (STAT0, 1) . . . . . . . . . . . . . . . . . . . . 62
CSIO Control/Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . 65

CSIO Transmit/Receive Data Register . . . . . . . . . . . . . . . . . 68
Timer Data Register Channel 0L . . . . . . . . . . . . . . . . . . . . . 68
Timer Data Register Channel 0H . . . . . . . . . . . . . . . . . . . . . 69
Timer Reload Register 0L . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Timer Reload Register 0H . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Timer Control Register (TCR) . . . . . . . . . . . . . . . . . . . . . . . . . . 70
ASCI Extension Control Register Channels 0 and 1 . . . . . . . . . 72

ASEXT0 and ASEXT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Timer Data Register Channel 1L . . . . . . . . . . . . . . . . . . . . . 74
Timer Data Register Channel 1H . . . . . . . . . . . . . . . . . . . . . 75
Timer Reload Register Channel 1L . . . . . . . . . . . . . . . . . . . 75
Timer Reload Register Channel 1L . . . . . . . . . . . . . . . . . . . 76
Free Running Counter I/O Address = 18H . . . . . . . . . . . . . . 76

DMA Source Address Register Channel 0 . . . . . . . . . . . . . . . . . 77

DMA Source Address Register, Channel 0L . . . . . . . . . . . . 78
DMA Source Address Register, Channel 0H . . . . . . . . . . . . 78
DMA Source Address Register Channel 0B . . . . . . . . . . . . . 79

DMA Destination Address Register Channel 0 . . . . . . . . . . . . . 79

DMA Destination Address Register Channel 0L . . . . . . . . . 80
DMA Destination Address Register Channel 0H . . . . . . . . . 80
DMA Destination Address Register Channel 0B . . . . . . . . . 81

DMA Byte Count Register Channel 0 . . . . . . . . . . . . . . . . . . . . . 81

DMA Byte Count Register Channel 0L . . . . . . . . . . . . . . . . . 82
DMA Byte Count Register Channel 0H . . . . . . . . . . . . . . . . 82
DMA Byte Count Register Channel 1L . . . . . . . . . . . . . . . . . 83
DMA Byte Count Register Channel 0H . . . . . . . . . . . . . . . . 83

Z80180

Microprocessor Unit

Table of Contents

PS014002-0403

DMA Memory Address Register Channel 1 . . . . . . . . . . . . . . . . 83

DMA Memory Address Register, Channel 1L . . . . . . . . . . . 84
DMA Memory Address Register, Channel 1H . . . . . . . . . . . 84

DMA I/O Address Register Channel 1 . . . . . . . . . . . . . . . . . . . . 85

DMA I/O Address Register Channel 1L . . . . . . . . . . . . . . . . 86
DMA I/O Address Register Channel 1H . . . . . . . . . . . . . . . . 86
DMA I/O Address Register Channel 1B . . . . . . . . . . . . . . . . 87
DMA Status Register (DSTAT) . . . . . . . . . . . . . . . . . . . . . . 87
Mnemonic DSTAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
DMA Mode Register (DMODE) . . . . . . . . . . . . . . . . . . . . . . 89
Mnemonic DMODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

DMA/WAIT Control Register (DCNTL) . . . . . . . . . . . . . . . . . . . . 92
Interrupt Vector Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Mnemonic: IL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Int/TRAP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Mnemonics ITC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Refresh Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Mnemonic RCR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

MMU Common Base Register . . . . . . . . . . . . . . . . . . . . . . . . . 101

Mnemonic CBR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

MMU Bank Base Register (BBR) . . . . . . . . . . . . . . . . . . . . . . . 102

Mnemonic BBR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

MMU Common/Bank Area Register (CBAR) . . . . . . . . . . . . . . 103

Mnemonic CBAR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Operation Mode Control Register . . . . . . . . . . . . . . . . . . . . . . 104

Mnemonic OMCR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

I/O Control Register (ICR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Z80180

Microprocessor Unit

List of Figures

PS014003-0603

vii

List of Figures

Figure 1. Z80180 Functional Block Diagram . . . . . . . . . . . . . . . 3
Figure 2. Z80180 64-Pin Dip Configuration . . . . . . . . . . . . . . . . 4
Figure 3. Z80180 68-Pin PLCC Configuration . . . . . . . . . . . . . . 5
Figure 4. Z80180 80-Pin QFP Configuration . . . . . . . . . . . . . . . 6
Figure 5. Timer Initialization, Count Down, and Reload Timing 19
Figure 6. Timer Data Register . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 7. CSIO Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 8. Operating Control Register (OMCR:

I/O Address = 3Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 9. RETI Instruction Sequence with MIE = 0 . . . . . . . . . 23
Figure 10. M1 Temporary Enable Timing . . . . . . . . . . . . . . . . . 24
Figure 11. I/O

READ

and

Write

Cycles with IOC = 1 . . . . . . . . . 24

Figure 12. I/O

READ

and Write Cycles with IOC = 0 . . . . . . . . . 25

Figure 13. HALT Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 14. SLEEP Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 15. AC Load Capacitance Parameters . . . . . . . . . . . . . . 29
Figure 16. CPU Timing (Op Code Fetch, I/O Write,

and I/O Read Cycles)

Figure 17. CPU Timing (

INT0

Acknowledge Cycle,

Refresh Cycle) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 18. CPU Timing (

IOC

= 0) (I/O Read Cycle,

I/O Write Cycle) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 19. DMA Control Signals . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 20. E Clock Timing (Memory R/W Cycle, I/O R/W Cycle) 48
Figure 21. E Clock Timing (Bus Release, Sleep, System Stop

Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 22. E Clock Timing (P

WEL

and P

WEH

Minimum Timing) . 49

Figure 23. Timer Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . 49

Z80180
Microprocessor Unit

PS014002-0403

List of Figures

viii

Figure 24.

SLEEP

Execution Cycle . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 25. CSIO Receive/Transmit Timing . . . . . . . . . . . . . . . . 51
Figure 26. Rise Time and Fall Times . . . . . . . . . . . . . . . . . . . . . 52
Figure 27. ASCI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 28. ASCI Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 29. ASCI Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 30. ASCI Receive Register Channel 0 . . . . . . . . . . . . . . 56
Figure 31. ASCI Receive Register Channel 1R . . . . . . . . . . . . . 56
Figure 32. ASCI Channel Control Register A . . . . . . . . . . . . . . 57
Figure 33. ASCI Channel Control Register B . . . . . . . . . . . . . . 60
Figure 34. ASCI Status Registers . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 35. CSIO Control Register . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 36. ASCI Receive Register Channel 1R . . . . . . . . . . . . . 68
Figure 37. ASCI Receive Register Channel 1R . . . . . . . . . . . . . 68
Figure 38. Timer Data Register Channel High . . . . . . . . . . . . . . 69
Figure 39. Timer Reload Register Low . . . . . . . . . . . . . . . . . . . 69
Figure 40. Timer Reload Register . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 41. Timer Control Register (TCR: I/O Address = 10h) . . 70
Figure 42. ASCI Extension Control Registers, Channel 0 and 1 72
Figure 43. Timer Data Register . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 44. Timer Data Register . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 45. Timer Data Register . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 46. Timer Data Register . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 47. Timer Data Register . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 48. DMA Channel 0L . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 49. DMA Channel 0H . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 50. DMA Channel 0B . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 51. DMA Destination Address Register Channel 0L . . . . 80
Figure 52. DMA Destination Address Register Channel 0H . . . 80
Figure 53. DMA Destination Address Register Channel 0B . . . 81

Z80180

Microprocessor Unit

List of Figures

PS014003-0603

Figure 54. DMA Byte Count Register 0L . . . . . . . . . . . . . . . . . . 82
Figure 55. DMA Byte Count Register 0H . . . . . . . . . . . . . . . . . . 82
Figure 56. DMA Byte Count Register 1L . . . . . . . . . . . . . . . . . . 83
Figure 57. DMA Byte Count Register 0H . . . . . . . . . . . . . . . . . . 83
Figure 58. DMA Memory Address Register, Channel 1L . . . . . . 84
Figure 59. DMA Memory Address Register, Channel 1H . . . . . 84
Figure 60. DMA Memory Address Register, Channel 1B . . . . . 85
Figure 61. IAR MS Byte Register (IARIB: I/O Address 2Dh . . . 85
Figure 62. DMA I/O Address Register Channel 1L . . . . . . . . . . 86
Figure 63. DMA I/O Address Register Channel 1H . . . . . . . . . . 86
Figure 64. DMA I/O Address Register Channel 1B . . . . . . . . . . 87
Figure 65. DMA Status Register (DSTAT: I/O Address = 30h) . 87
Figure 66. DMA Mode Register (DMODE: I/O Address = 31h) . 90
Figure 67. DMA/WAIT Control Register (DCNTL: I/O Address

= 32h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Figure 68. Interrupt Vector Low Register (IL: I/O Address

= 33h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Figure 69. Int/TRAP Control Register . . . . . . . . . . . . . . . . . . . . 95
Figure 70. TRAP Timing--2nd Op Code Undefined . . . . . . . . . 97
Figure 71. TRAP Timing--3rd Op Code Undefined . . . . . . . . . . 98
Figure 72. Refresh Control Register (RCA: I/O Address = 36h) 99
Figure 73. MMU Bank Base Register (BBR: I/O Address

= 39h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Figure 74. MMU Bank Base Register (BBR: I/O Address

= 39h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Figure 75. MMU Common/Bank Area Register (CBAR: I/O

Address = 3 AH . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Figure 76. Operating Control Register(OMCR: I/O Address

= 3Eh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Figure 77. RETI Instruction Sequence with MIE=0 . . . . . . . . . 105
Figure 78. I/O Control Register (ICR: I/O Address = 3Fh) . . . . 106

Z80180

Microprocessor Unit

List of Tables

PS014003-0603

List of Tables

Table 1. Power Connection Conventions . . . . . . . . . . . . . . . . . . . 2
Table 2. Pin Status During RESET BUSACK and SLEEP . . . . . . 7
Table 3. Status Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 4. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . 30
Table 5. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 6. Z80180-6 AC Characteristics . . . . . . . . . . . . . . . . . . . . 32
Table 7. Z80180-8 AC Characteristics . . . . . . . . . . . . . . . . . . . . 35
Table 8. Z80180-10 AC Characteristics . . . . . . . . . . . . . . . . . . . 39
Table 9. ASCI Data Formats Mode 2, 1, 0 . . . . . . . . . . . . . . . . . 59
Table 10. Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 11. Divide Ratio. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 12. CSIO Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . 67
Table 13. Timer Output Control. . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 14. DMA Transfer Requests . . . . . . . . . . . . . . . . . . . . . . . 81
Table 15. Channel 0 Destination. . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 16. Channel 0 Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 17. Channel 1 Transfer Mode . . . . . . . . . . . . . . . . . . . . . . 94
Table 18. DRAM Refresh Intervals . . . . . . . . . . . . . . . . . . . . . . 100
Table 19. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 111

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

Overview

Features

Code Compatible with ZiLOG Z80

CPU

Extended Instructions

Two DMA Channels

Low Power-Down Modes

On-chip Interrupt Controllers

Three On-Chip Wait-State Generators

On-Chip Oscillator/Generator

Expanded MMU Addressing (up to 1 MB)

Clocked Serial I/O Port

Two 16-Bit Counter/Timers

Two UARTs

Clock Speeds: 6, 8, and 10 MHz

6-MHz version supports 6.144-MHz CPU Clock Operation

Operating Range: 5V

Operating Temperature Range: 0ºC to +70ºC

Three Packaging Styles

68-Pin PLCC

64-Pin DIP

80-Pin QFP

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

General Description

The Z80180

is an 8-bit Microprocessor Unit (MPU) which pro-

vides the benefits of reduced system costs while also providing full
backward compatibility with existing ZiLOG Z80 devices.

Reduced system costs are obtained by incorporating several key
system functions on-chip with the CPU. These key functions
include I/O devices such as DMA, UART, and timer channels. Also
included on-chip are wait-state generators, a clock oscillator, and
an interrupt controller.

The Z80180 is housed in 80-pin QFP, 68-pin PLCC, and 64-pin DIP
packages.

All Signals with an overline are active Low. For
example, B/W, in which WORD is active Low);
and B/W, in which BYTE is active Low.

Power connections follow conventional descriptions as shown in
Table 1.

Table 1. Power Connection Conventions

Connection

Circuit

Device

Power

Ground

GND

Note:

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

Z80180 68-Pin PLCC Pin Configuration

Figure 3. Z80180 68-Pin PLCC Configuration

WAI

PHI

RFS

INT0
INT1
INT2

A0
A1
A2
A3

A4
A5
A6
A7
A8
A9

A10

A11

Z80180

68-Pin PLCC

HALT
TENDi
DREQi
CKS
RXS/

CTS1

TXS
CKA1/

TEND0

RXA1
TEST
TXA1
CKA0/

DREQ0

RXA0
TXA0
DCD0
CTS0
RTS0
D7

A12

A13

A14

A15

A16

A17

A18/T

A19

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

Figure 4. Z80180 80-Pin QFP Configuration

IORQ

MREQ

PHI

XTAL

N/C

EXTAL

WAIT

BUSACK

BUSREQ

RESET

NMI

N/C

INT

N/C

L
T

ND1

DRE

/
CT

/
T

/
DRE

DCD0

Z80180

80-Pin QFP

D5
D4
D3
D2
D1
D0
V

A19
V

A18/T

OUT

NC
A17
A16
A15
A14
A13

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

Table 2. Pin Status During RESET BUSACK and SLEEP

Pin Number and
Package Type

Default
Function

Secondary
Function

Pin Status

QFP PLCC

DIP

RESET BUSACK

SLEEP

NMI

INT0

INT1

INT2

GND

A10

A11

A12

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

A13

A14

A15

A16

A17

A18

OUT

A19

GND

RTS0

OUT

CTS0

OUT

DCD0

TXA0

OUT

RXA0

Table 2. Pin Status During RESET BUSACK and SLEEP (continued)

Pin Number and
Package Type

Default
Function

Secondary
Function

Pin Status

QFP PLCC

DIP

RESET BUSACK

SLEEP

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

CKA0

DREQ0

OUT

TXA1

OUT

TEST

RXA1

CKA1

TEND0

TXS

OUT

RXS

CTS1

CKS

I/O

DREQ1

TEND1

OUT

HALT

RFSH

OUT

IORQ

MREQ

OUT

PHI

OUT

GND

XTAL

OUT

Table 2. Pin Status During RESET BUSACK and SLEEP (continued)

Pin Number and
Package Type

Default
Function

Secondary
Function

Pin Status

QFP PLCC

DIP

RESET BUSACK

SLEEP

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

Pin Descriptions

0A19. Address Bus (output, active High, 3-state).

form a

20-bit address bus. The Address Bus provides the address for
memory data bus exchanges, up to 1 MB, and I/O data bus
exchanges, up to 64 KB. The address bus enters a high-imped-
ance state during reset and external bus acknowledge cycles.
Address line

A18

is multiplexed with the output of PRT channel 1

(

OUT

, selected as address output on reset) and address line

A19

not available in DIP versions of the Z80180.

BUSACK.

Bus Acknowledge (output, active Low).

BUSACK

indi-

cates the requesting device, the MPU address and data bus, and
some control signals that enter their high-impedance state.

BUSREQ.

Bus Request (input, active Low). This input is used by

external devices (such as DMA controllers) to request access to
the system bus. This request demands a higher priority than

NMI

and is always recognized at the end of the current machine cycle.
This signal stops the CPU from executing further instructions and

EXTAL

WAIT

BUSACK

OUT

BUSREQ

RESET

Table 2. Pin Status During RESET BUSACK and SLEEP (continued)

Pin Number and
Package Type

Default
Function

Secondary
Function

Pin Status

QFP PLCC

DIP

RESET BUSACK

SLEEP

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

places address and data buses, and other control signals, into the
high-impedance state.

CKA0, CKA1

. Asynchronous Clock 0 and 1 (bidirectional, active

High). When in output mode, these pins are the transmit and
receive clock outputs from the ASCI baud rate generators. When in
input mode, these pins serve as the external clock inputs for the
ASCI baud rate generators.

CKA0

is multiplexed with

DREQ0

, and

CKA1

is multiplexed with

TEND0

CKS.

Serial Clock (bidirectional, active High). This line is the clock

for the

CSIO

channel.

CLOCK

. System Clock (output, active High). The output is used as

a reference clock for the MPU and the external system. The fre-
quency of this output is equal to one-half that of the crystal or input
clock frequency.

CTS0

CTS1.

Clear to send

and

(inputs, active Low). These lines

are modem control signals for the ASCI channels.

CTS1

is multi-

plexed with

RXS

D0D7

. Data Bus (bidirectional, active High, 3-state).

D0D7

consti-

tute an 8-bit bidirectional data bus, used for the transfer of informa-
tion to and from I/O and memory devices. The data bus enters the
high-impedance state during reset and external bus acknowledge
cycles.

DCD0

. Data Carrier Detect 0 (input, active Low). A programmable

modem control signal for ASCI channel 0.

DREQ0, DREQ1. DMA Request 0 and 1 (input, active Low).

DREQ

is used to request a DMA transfer from one of the on-chip DMA
channels. The DMA channels monitor these inputs to determine
when an external device is ready for a

READ

WRITE

operation.

These inputs can be programmed to be either level or edge
sensed.

DREQ0

is multiplexed with

CKA0

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

. Enable Clock (output, active High). Synchronous machine cycle

clock output during bus transactions.

EXTAL.

External Clock Crystal (input, active High). Crystal oscilla-

tor connections. An external clock can be input to the Z80180 on
this pin when a crystal is not used. This input is Schmitt-triggered.

HALT. HALT/SLEEP

(output, active Low). This output is asserted

after the CPU executes either the

HALT

SLEEP

instruction, and

is waiting for either nonmaskable or maskable interrupt before
operation can resume. It is also used with the

and

signals to

decode status of the CPU machine cycle.

INT0.

Maskable Interrupt Request 0 (input, active Low). This signal

is generated by external I/O devices. The CPU honors these
requests at the end of the current instruction cycle as long as the

NMI

and

BUSREQ

signals are inactive. The CPU acknowledges this

interrupt request with an interrupt acknowledge cycle. During this
cycle, both the

and

IORQ

signals become active.

INT1

INT2.

Maskable Interrupt Request 1 and 2 (inputs, active

Low). This signal is generated by external I/O devices. The CPU
honors these requests at the end of the current instruction cycle as
long as the

NMI

BUSREQ

, and

INT0

signals are inactive. The CPU

acknowledges these requests with an interrupt acknowledge cycle.
Unlike the acknowledgment for

INT0

, during this cycle neither the

IORQ

signals become active.

IORQ.

I/O Request (output, active Low, 3-state).

IORQ

indicates

that the address bus contains a valid I/O address for an I/O

READ

or I/O

WRITE

operation.

IORQ

is also generated, along with

during the acknowledgment of the

INT0

input signal to indicate that

an interrupt response vector can be placed onto the data bus. This
signal is analogous to the

IOE

signal of the Z64180.

M1.

Machine Cycle 1 (output, active Low). Together with

MREQ

indicates that the current cycle is the op code fetch cycle of and

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

instruction execution. Together with

IORQ

indicates that the

current cycle is for an interrupt acknowledge. It is also used with
the

HALT

and

signal to decode status of the CPU machine

cycle. This signal is analogous to the

LIR

signal of the Z64180.

MREQ.

Memory Request (output, active Low, 3-state).

MREQ

indi-

cates that the address bus holds a valid address for a memory

READ

or memory

WRITE

operation. This signal is analogous to the

signal of Z64180.

NMI.

Nonmaskable Interrupt (input, negative edge triggered).

NMI

demands a higher priority than

INT

and is always recognized at the

end of an instruction, regardless of the state of the interrupt enable
flip-flops. This signal forces CPU execution to continue at location

0066h

RD.

Op Code Reinitialized (output, active Low, 3-state).

indi-

cated that the CPU wants to read data from memory or an I/O
device. The addressed I/O or memory device should use this sig-
nal to gate data onto the CPU data bus.

RFSH.

Refresh (output, active Low). Together with

MREQ

RFSH

indicates that the current CPU machine cycle and the contents of
the address bus should be used for refresh of dynamic memories.
The low order 8 bits of the address bus (

A7A10

) contain the

refresh address. This signal is analogous to the

REF

signal of the

Z64180.

RTS0.

Request to Send 0 (output, active Low). A programmable

modem control signal for ASCI channel 0.

RXA0, RXA1.

Receive Data 0 and 1 (input, active High). These sig-

nals are the receive data to the ASCI channels.

RXS

. Clocked Serial Receive Data (input, active High). This line is

the receiver data for the

CSIO

channel.

RXS

is multiplexed with the

CTS1

signal for ASCI channel 1.

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

ST.

Status (output, active High). This signal is used with the

and

HALT

output to decode the status of the CPU machine cycle.

TEND0, TEND1.

Transfer End 0 and 1 (outputs, active Low). This

output is asserted active during the most recent

WRITE

cycle of a

DMA operation. It is used to indicate the end of the block transfer.

TEND0

is multiplexed with

CKA1

TEST

. Test (output, not in DIP version). This pin is for test and

should be left open.

TOUT.

Timer Out (output, active High).

OUT

is the pulse output

from PRT channel 1. This line is multiplexed with A18 of the
address bus.

TXA0, TXA1.

Transmit Data 0 and 1 (outputs, active High). These

signals are the transmitted data from the ASCI channels. Transmit-
ted data changes are with respect to the falling edge of the transmit
clock.

TXS.

Clocked Serial Transmit Data (output, active High). This line

is the transmitted data from the CSIO channel.

Table 3. Status Summary

HALT

Operation

CPU Operation (1st op code fetch)

CPU Operation (2nd op code and 3rd op code
fetch)

CPU Operation(MC except for op code fetch)

DMA Operation

HALT Mode

SLEEP Mode (including SYSTEM STOP Mode)

Notes:
X = Reserved.
MC = Machine Cycle.

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

WAIT.

Wait (input, active Low).

WAIT

indicated to the MPU that the

addressed memory or I/O devices are not ready for a data transfer.
This input is sampled on the falling edge of T2 (and subsequent
wait states). If the input is sampled Low, then the additional wait
states are inserted until the

WAIT

input is sampled high, at which

time execution continues.

WR. WRITE

(output, active Low, 3-state).

indicated that the

CPU data bus holds valid data to be stored at the addressed I/O or
memory location.

XTAL.

Crystal (input, active High). Crystal oscillator connection.

This pin should be left open if an external clock is used instead of a
crystal. The oscillator input is not a

TTL

level (see DC Characteris-

tics). Several pins are used for different conditions, depending on
the circumstance.

Multiplexed Pin Descriptions

Table 4: Multiplexed Pin Descriptions

Pin

Description

A18/T

OUT

During RESET, this pin is initialized as A18 pin. If either TOC1 or
TOC0 bit of the Timer Control Register (TCR) is set to 1, T

OUT

function is selected. If TOC1 and TOC0 are cleared to 0, A18 function
is selected.

CKA0/DREQ0

During RESET, this pin is initialized as CKA0 pin. If either DM1 or
SM1 in DMA Mode Register (DMODE) is set to 1, DREQ0 function is
always selected.

CKA1/TEND0

During RESET, this pin is initialized as CKA1 pin. If CKA1D bit in ASCI
control register ch1 (CNTLA1) is set to 1, TEND0 function is selected.
If CKA1D bit is set to 0, CKA1 function is selected.

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

Architecture

The Z180

combines a high-performance CPU core with a variety

of system and I/O resources useful in a broad range of applica-
tions. The CPU core consists of five functional blocks: clock gener-
ator, bus state controller, Interrupt controller, memory management
unit (MMU), and the central processing unit (CPU). The integrated
I/O resources make up the remaining four function blocks: direct
memory access (DMA) control (2 channels), asynchronous serial
communication interface (ASCI, 2 channels) programmable reload
timers (PRT, 2 channels), and a clock serial I/O (CSIO) channel.

Clock Generator

. Generates system clock from an external crystal

or clock input. The external clock is divided by two or one and pro-
vided to both internal and external devices.

Bus State Controller.

This logic performs all of the status and bus

control activity associated with both the CPU and some on-chip
peripherals. Included are wait-state timing, reset cycles, DRAM
refresh, and DMA bus exchanges.

Interrupt Controller.

This logic monitors and prioritizes the variety

of internal and external interrupts and traps to provide the correct
responses from the CPU. To maintain compatibility with the Z80

CPU, three different interrupts modes are supported.

Memory Management Unit.

The MMU allows the user to map the

memory used by the CPU (logically only 64 KB) into the 1-MB
addressing range supported by the Z80180. The organization of
the MMU object code allows maintenance compatibility with the
Z80 CPU, while offering access to an extended memory space.
This organization is achieved by using an effective common area-
banked area scheme.

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

Central Processing Unit

. The CPU is microcoded to provide a core

that is object-code compatible with the Z80 CPU. It also provides a
superset of the Z80 instruction set, including 8-bit multiply. The
core is modified to allow many of the instructions to execute in
fewer clock cycles.

DMA Controller

. The DMA controller provides high speed transfers

between memory and I/O devices. Transfer operations supported
are memory-to-memory, memory to/from I/O, and I/O-to-I/O. Trans-
fer modes supported are request, burst, and cycle steal. DMA
transfers can access the full 1 MB address range with a block
length up to 64 KB, and can cross over 64K boundaries.

Asynchronous Serial Communication Interface (ASC)

. The ASCI

logic provides two individual full-duplex UARTs. Each channel
includes a programmable baud rate generator and modem control
signals. The ASCI channels can also support a multiprocessor
communication format as well as break detection and generation.

Programmable Reload Timers (PRT)

. This logic consists of two sep-

arate channels, each containing a 16-bit counter (timer) and count
reload register. The time base for the counters is derived from the
system clock (divided by 20) before reaching the counter. PRT
channel 1 provides an optional output to allow for waveform gener-
ation.

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

Figure 5. Timer Initialization, Count Down, and Reload Timing

FFFFh

0004h

0003h 0002h 0001h 0000h 0003h 0002h 0001h 0000h 0003h

Timer Data Register

WRITE (0004h)

Timer Data

Timer Reload

TDE Flag

TIF Flag

RESET

20 f

0 < t < 20 f

Timer Reload Register WRITE (0003h)

FFFFh

0003h

Reload

WRITE

a 1

to TDE

Timer Data Register READ

Timer Control Requestor READ

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

Figure 6. Timer Data Register

Clocked Serial I/O (CSIO). The

CSIO

channel provides a half-

duplex serial transmitter and receiver. This channel can be used for
simple high-speed data connection to another microprocessor or
microcomputer.

TRDR

is used for both

CSIO

transmission and

reception. The system design must ensure that the constraints of
half-duplex operation are met. Transmit and Receive operations
cannot occur simultaneously. For example, if a

CSIO

transmission

is attempted while the

CSIO

is receiving data, a

CSIO

does not

work.

TRDR

is not buffered. Attempting to perform a

CSIO

transmit while the previous transmit data is

still being shifted out causes the shift data to be
immediately updated, corrupting the transmit
operation in progress. Reading

TRDR

while a

transmit or receive is in progress should be
avoided.

Timer Data

Reg. = 0001h

Timer Data

Reg. = 0000h

OUT

Note:

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

Figure 7. CSIO Block Diagram

Operation Modes

Z80

versus 64180 Compatibility

The Z80180 is descended from two different ancestor processors,
ZiLOG's original Z80 and the Hitachi 64180. The Operating Mode
Control Register (OMCR), illustrated in Figure 8, can be pro-
grammed to select between certain Z80 and 64180 differences.

Internal Address/Data Bus

CSIO Transmit/Receive

Data Register:

TRDR (8)

CSIO Control Register:

CNTR (8)

Baud Rate

Generator

TXS
RXS

CKS

Interrupt Request

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

Figure 8. Operating Control Register (OMCR: I/O Address = 3Eh)

M1E (M1 Enable)

This bit controls the

output and is set to a

during

RESET

When

M1E = 1

, the

output is asserted Low during the op code

fetch cycle, the

INT0

acknowledge cycle, and the first machine

cycle of the

NMI

acknowledge.

On the Z80180, this choice makes the processor fetch a

RETI

instruction one time only, and when fetching a

RETI

from zero-wait-

state memory uses three clock machine cycles, which are not fully
Z80-timing compatible but are compatible with the on-chip CTCs.

When

M1E = 0

, the processor does not drive

Low during instruc-

tion fetch cycles. After fetching a

RETI

instruction one time only,

with normal timing, the processor goes back and refetches the
instruction using fully Z80-compatible cycles that include driving

Low. Some external Z80 peripherals may require properly decoded

RETI

instructions. Figure 9 illustrates the

RETI

sequence when

M1E

= 0

Reserved

D6 D5 --

IOC (R/W)

M1TE (W)
M1E (R/W)

-- -- -- --

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

Figure 9. RETI Instruction Sequence with MIE = 0

M1TE (M1 Temporary Enable)

This bit controls the temporary

assertion of the

signal. It is always read back as a

and is set

during

RESET

When

M1E

is set to

to accommodate certain external Z80 periph-

eral(s), those same device(s) may require a pulse on M1 after pro-
gramming certain of their registers to complete the function being
programmed.

For example, when a control word is written to the Z80

PIO

enable interrupts, no enable actually takes place until the

PIO

sees

an active

signal. When

M1TE = 1

, there is no change in the

operation of the

signal and

M1E

controls its function. When

M1TE = 0

, the

output is asserted during the next op code fetch

cycle regardless of the state programmed into the

M1E

bit. This

instance is only momentary (one time only) and the user is not
required to preprogram a

to disable the function (see Figure 10).

)

PC+1

EDh

4Dh

EDh

4Dh

MREQ

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

Figure 10. M1 Temporary Enable Timing

IOC

This bit controls the timing of the

IORQ

and

signals. It is set

RESET

. When

IOC

= 1

, the

IORQ

and

signals function the

same as the Z64180 (Figure 11).

Figure 11. I/O READ and WRITE Cycles with IOC = 1

When

IOC = 0

, the timing of the

IORQ

and

signals match the tim-

ing of the Z80. The

IORQ

and

signals go active as a result of the

rising edge of

. (Figure 12.)

Op Code Fetch

WRITE into OMCR

IORQ

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

Figure 12. I/O READ and WRITE Cycles with IOC = 0

HALT and Low-Power Operating Modes.

The Z80180 can operate

in five modes with respect to activity and power consumption:

Normal Operation

HALT

mode

IOSTOP

mode

SLEEP

mode

SYSTEM STOP mode

Normal Operation.

The Z80180 processor is fetching and running a

program. All enabled functions and portions of the device are
active, and the

HALT

pin is High.

HALT Mode.

This mode is entered by the

HALT

instruction. There-

after, the Z80180 processor continually fetches the following op
code but does not execute it, and drives the

HALT

and

pins

all Low. The oscillator and

PHI

pin remain active, interrupts and bus

granting to external masters, and DRAM refresh can occur and all

IORQ

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

on-chip I/O devices continue to operate including the DMA chan-
nels.

The Z80180 leaves

HALT

mode in response to a Low on

RESET

, on

to an interrupt from an enabled on-chip source, an external request
on

NMI

, or an enabled external request on

INT0

INT1

, or

INT2

. In

case of an interrupt, the return address is the instruction following
the

HALT

instruction; at that point the program can either branch

back to the

HALT

instruction to wait for another interrupt, or can

examine the new state of the system/application and respond
appropriately.

Figure 13. HALT Timing

HALT Op Code Fetch Cycle

HALT Mode

INT

, NMI

HALT

MREQ

Interrupt

Acknowledge Cycle

HALT Op Code Address

HALT Op Code Address + 1

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

SLEEP Mode Enter

SLEEP

mode by keeping the

IOSTOP

bit (

ICR5

)

bits

and

of the CPU Control Register (

CCR3

CCR6

) all zero and

executing the

SLEEP

instruction. The oscillator and

PHI

output con-

tinue operating, but are blocked from the CPU core and DMA chan-
nels to reduce power consumption. DRAM refresh stops but
interrupts and granting to external master can occur. Except when
the bus is granted to an external master,

A190

and all control sig-

nals except

HALT

are maintained High.

HALT

is Low. I/O operations

continue as before the

SLEEP

instruction, except for the DMA

channels.

The Z80180 leaves

SLEEP

mode in response to a Low on

RESET

an interrupt request from an on-chip source, an external request on

NMI

, or an external request on

INT0

INT1

, or

INT2

If an interrupt source is individually disabled, it cannot bring the
Z80180 out of

SLEEP

mode. If an interrupt source is individually

enabled, and the

IEF

bit is

so that interrupts are globally enabled

(by an

instruction), the highest priority active interrupt occurs,

with the return address being the instruction after the

SLEEP

instruction. If an interrupt source is individually enabled, but the

IEF

bit is

so that interrupts are globally disabled (by a

instruction),

the Z80180 leaves

SLEEP

mode by simply executing the following

instruction(s).

This provides a technique for synchronization with high- speed
external events without incurring the latency imposed by an inter-
rupt response sequence. Figure 14 shows the timing for exiting

SLEEP

mode due to an interrupt request.

The Z80180 takes about 1.5 clocks to restart.

Note:

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

Figure 14. SLEEP Timing

IOSTOP Mode. IOSTOP

mode is entered by setting the

IOSTOP

bit

of the I/O Control Register (

ICR

) to

. In this case, on-chip I/O

(

ASCI

CSIO

PRT

) stops operating. However, the CPU continues to

operate. Recovery from

IOSTOP

mode is by resetting the

IOSTOP

bit in

ICR

SYSTEM STOP Mode.

SYSTEM STOP

mode is the combination of

SLEEP

and

IOSTOP

modes.

SYSTEM STOP

mode is entered by set-

ting the

IOSTOP

bit in

ICR

followed by execution of the

SLEEP

instruction. In this mode, on-chip I/O and CPU stop operating,
reducing power consumption, but the

PHI

output continues to oper-

ate. Recovery from

SYSTEM STOP

mode is the same as recovery

from

SLEEP

mode except that internal I/O sources (disabled by

IOSTOP

) cannot generate a recovery interrupt.

SLEEP 2nd Op Code

SLEEP Mode

INT

, NMI

HALT

Op Code Fetch or Interrupt

Acknowledge Cycle

SLEEP 2nd Op Code Address

FFFFFh

Fetch Cycle

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

Standard Test Conditions

The DC Characteristics section applies to the following standard
test conditions, unless otherwise noted. All voltages are referenced
to

GND

(0V). Positive current flows in to the referenced pin.

All AC parameters assume a load capacitance of 100 pF. Add 10
ns delay for each 50 pF increase in load up to a maximum of 200
pF for the data bus and 100 pF for the address and control lines.
AC timing measurements are referenced to 1.5 volts (except for

CLOCK

, which is referenced to the 10% and 90% points). The

Ordering Information section lists temperature ranges and product
numbers. Package drawings are in the Package Information sec-
tion. See Figure 15.

Figure 15. AC Load Capacitance Parameters

+5 V

From Output

100 pF

Under Test

250

µm A

2.1k

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

Absolute Maximum Ratings

Permanent LSI damage may occur if maximum
ratings are exceeded. Normal operation should
be under recommended operating conditions. If
these conditions are exceeded, it could affect
reliability of LSI.

DC Characteristics

Table 5. Absolute Maximum Ratings

Item

Symbol

Value

Unit

Supply Voltage

0.3 ~ +7.0

Input Voltage

0.3 ~ V

+0.3

Operating Temperature

opr

0 ~ 70

°C

Extended Temperature

ext

40 ~ 85

°C

Storage Temperature

stg

55 ~ +150

°C

Table 6. DC Characteristics

Sym. Item

Condition

Min.

Typ. Max.

Unit

IH1

Input

H Voltage RESET,

EXTAL,

NMI

0.6

+0.3 V

IH2

Input

H Voltage Except

RESET, EXTAL, NMI

2.0

+0.3 V

Note: *V

IHmin

= V

1.0V, V

ILmax

= 0.8V (all output terminals are at no load); V

= 5.0V.

Note: V

= 5V + 10%, V

= 0V over specified temperature range, unless otherwise noted

Note:

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

AC Characteristics

Tables 7, 8, and 9 provide AC characteristics for the Z80180-6,
Z80180-8, and Z80180-10 respectively. V

= 5V + 10%, V

0V, T

0°C to +70°C, unless otherwise noted.

IL1

Input

L Voltage RESET,

EXTAL,

NMI

0.3

0.6

IL2

Input

L Voltage Except

RESET, EXTAL, NMI

0.3

0.8

Outputs

H Voltage All

outputs

= 200µA

2.4

= 20µA

1.2

Outputs

L Voltage All

outputs

= 2.2µA

0.45

Input Leakage Current
All Inputs Except XTAL,
EXTAL

= 0.5 ~ V

0.5

1.0

µA

Three State Leakage
Current

= 0.5 ~ V

0.5

1.0

µA

CC*

Power Dissipation*
(Normal Operation)

F = 6 MHz

F = 8 MHz

F = 10 MHz**

Power Dissipation*
(SYSTEM STOP
mode)

F = 6 MHz

3.8

12.5

F = 8 MHz

F = 10 MHz**

6.3

17.5

Pin Capacitance

= 0V,

f = 1

MHzT

= 25° C

Table 6. DC Characteristics (continued)

Sym. Item

Condition

Min.

Typ. Max.

Unit

Note: *V

IHmin

= V

1.0V, V

ILmax

= 0.8V (all output terminals are at no load); V

= 5.0V.

Note: V

= 5V + 10%, V

= 0V over specified temperature range, unless otherwise noted

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

Table 7. Z80180-6 AC Characteristics

No. Symbol Item

Z80180-6

Unit

Min. Max.

cyc

Clock Cycle Time

162

2000

CHW

Clock

H Pulse Width

CLW

Clock

L Pulse Width

Clock Fall Time

Clock Rise Time

ØRise to Address Valid Delay

Address Valid to MREQ Fall or IORQ

Fall)

MED1

Ø Fall to MREQ Fall

Delay

RDD1

Ø Fall to

RD Fall

Delay

IOC = 1

Ø Rise to

RD Rise

Delay

IOC = 0

M1D1

Ø Rise to

M1 Fall

Delay

Address Hold Time from
(MREQ,

IOREQ, RD, WR)

MED2

Ø Fall to MREQ Rise

Delay

RDD2

Ø Fall to

RD Rise

Delay

M1D2

Ø Rise to

M1 Rise

Delay

DRS

Data Read Set-up Time

DRH

Data Read Hold Time

STD1

Ø Fall to ST Fall

Delay

STD2

Ø Fall to ST Rise

Delay

WAIT Set-up Time to Ø Fall

WAIT Hold Time from Ø Fall

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

WDZ

Ø Rise to Data Float Delay

WRD1

Ø Rise to

WR Fall

Delay

WDD

Ø Fall to

WRITE Data Delay Time

WDS

WRITE Data Set-up Time to WR Fall

WRD2

Ø Fall to

WR Rise

Delay

WRP

WR Pulse Width

170

26a

WR Pulse Width (I/O WRITE Cycle)

332

WDH

WRITE Data Hold Time from (WR Rise

)

IOD1

Ø Fall to

IORQ Fall

Delay

IOC = 1

Ø Rise to

IORQ Fall

Delay

IOC = 1

IOD2

Ø Fall to

IORQ Rise

Delay

IOD3

M1 Fall to IORQFall

Delay

340

INTS

INT Set-up Time to Ø Fall

INTS

INT Hold Time from Ø Fall

NMIW

NMI Pulse Width

120

BRS

BUSREQ Set-up Time to Ø Fall

BRH

BUSREQ Hold Time from Ø Fall

BAD1

Ø Rise to

BUSACK Fall

Delay

BAD2

Ø Fall to

BUSACK Rise

Delay

BZD

Ø Rise to Bus Floating Delay Time

125

MEWH

MREQ Pulse Width (High)

110

MEWL

MREQ Pulse Width (Low)

125

RFD1

Ø Rise to

RFSH Fall Delay

RFD2

Ø Rise to

RFSHRise Delay

HAD1

Ø Rise to

HALT Fall Delay

HAD2

Ø Rise to

HALTRise Delay

DRQS

/DREQi Set-up Time to Ø Rise

DRQH

/DREQi Hold Time from Ø Rise

Table 7. Z80180-6 AC Characteristics (continued)

No. Symbol Item

Z80180-6

Unit

Min. Max.

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

TED1

Ø Fall to

TENDi Fall Delay

TED2

Ø Fall to

TENDiRise Delay

ED1

Ø Rise to E Rise Delay

ED2

Ø Fall or Rise to E Fall Delay

WEH

E Pulse Width (High)

WEL

E Pulse Width (Low)

180

Enable Rise Time

Enable Fall Time

TOD

Ø Fall to Timer Output Delay

300

STDI

CSIO Transmit Data Delay Time (Internal Clock
Operation)

200

STDE

CSIO Transmit Data Delay Time (External Clock
Operation)

7.5tcy
c
+300

SRSI

CSIO Receive Data Set-up Time (Internal Clock
Operation)

tcyc

SRHI

CSIO Receive Data Hold Time (Internal Clock
Operation)

tcyc

SRSE

CSIO Receive Data Set-up Time (External Clock
Operation)

tcyc

SRHE

CSIO Receive Data Hold Time (External Clock
Operation)

tcyc

RES

RESET Set-up Time to Ø Fall

120

REH

RESET Hold Time from Ø Fall

OSC

Oscillator Stabilization Time

EXr

External Clock Rise Time (EXTAL)

EXf

External Clock Fall Time (EXTAL)

RESET Rise Time

RESET Fall Time

Table 7. Z80180-6 AC Characteristics (continued)

No. Symbol Item

Z80180-6

Unit

Min. Max.

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

Input Rise Time (except EXTAL,

RESET)

100

Input Fall Time (except EXTAL,

RESET)

100

Table 8. Z80180-8 AC Characteristics

No. Symbol Item

Z80180-8

Unit

Min.

Max.

cyc

Clock Cycle Time

125

2000 ns

CHW

Clock

H Pulse Width

CLW

Clock

L Pulse Width

Clock Fall Time

Clock Rise Time

ØRise to Address Valid Delay

Address Valid to MREQ Fall or IORQ

Fall)

MED1

Ø Fall to MREQ Fall

Delay

RDD1

Ø Fall to

RD Fall

Delay

IOC = 1

Ø Rise to

RD Rise

Delay

IOC = 0

M1D1

Ø Rise to

M1 Fall

Delay

Address Hold Time from
(MREQ,

IOREQ, RD, WR)

MED2

Ø Fall to MREQ Rise

Delay

RDD2

Ø Fall to

RD Rise

Delay

Table 7. Z80180-6 AC Characteristics (continued)

No. Symbol Item

Z80180-6

Unit

Min. Max.

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

M1D2

Ø Rise to

M1 Rise

Delay

70*

DRS

Data Read Set-up Time

DRH

Data Read Hold Time

STD1

Ø Fall to ST Fall

Delay

STD2

Ø Fall to ST Rise

Delay

WAIT Set-up Time to Ø Fall

WAIT Hold Time from Ø Fall

WDZ

Ø Rise to Data Float Delay

WRD1

Ø Rise to

WR Fall

Delay

WDD

Ø Fall to

WRITE Data Delay Time

WDS

WRITE Data Set-up Time to WR Fall

WRD2

Ø Fall to

WR Rise

Delay

WRP

WR Pulse Width

130

26a

WR Pulse Width (I/O WRITE Cycle)

255

WDH

WRITE Data Hold Time from (WR Rise

)

IOD1

Ø Fall to

IORQ Fall

Delay

IOC = 1

Ø Rise to

IORQ Fall

Delay

IOC = 1

IOD2

Ø Fall to

IORQ Rise

Delay

IOD3

M1 Fall to IORQFall

Delay

250

INTS

INT Set-up Time to Ø Fall

INTS

INT Hold Time from Ø Fall

Table 8. Z80180-8 AC Characteristics (continued)

No. Symbol Item

Z80180-8

Unit

Min.

Max.

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

NMIW

NMI Pulse Width

100

BRS

BUSREQ Set-up Time to Ø Fall

BRH

BUSREQ Hold Time from Ø Fall

BAD1

Ø Rise to

BUSACK Fall

Delay

BAD2

Ø Fall to

BUSACK Rise

Delay

BZD

Ø Rise to Bus Floating Delay Time

MEWH

MREQ Pulse Width (High)

MEWL

MREQ Pulse Width (Low)

100

RFD1

Ø Rise to

RFSH Fall Delay

RFD2

Ø Rise to

RFSHRise Delay

HAD1

Ø Rise to

HALT Fall Delay

HAD2

Ø Rise to

HALTRise Delay

DRQS

/DREQi Set-up Time to Ø Rise

DRQH

/DREQi Hold Time from Ø Rise

TED1

Ø Fall to

TENDi Fall Delay

TED2

Ø Fall to

TENDiRise Delay

ED1

Ø Rise to E Rise Delay

ED2

Ø Fall or Rise to E Fall Delay

WEH

E Pulse Width (High)

WEL

E Pulse Width (Low)

130

Enable Rise Time

Table 8. Z80180-8 AC Characteristics (continued)

No. Symbol Item

Z80180-8

Unit

Min.

Max.

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

Enable Fall Time

TOD

Ø Fall to Timer Output Delay

200

STDI

CSIO Transmit Data Delay Time (Internal Clock
Operation)

200

STDE

CSIO Transmit Data Delay Time (External Clock
Operation)

7.5tcy
c
+200

SRSI

CSIO Receive Data Set-up Time (Internal Clock
Operation)

tcyc

SRHI

CSIO Receive Data Hold Time (Internal Clock
Operation)

tcyc

SRSE

CSIO Receive Data Set-up Time (External Clock
Operation)

tcyc

SRHE

CSIO Receive Data Hold Time (External Clock
Operation)

tcyc

RES

RESET Set-up Time to Ø Fall

100

REH

RESET Hold Time from Ø Fall

OSC

Oscillator Stabilization Time

EXr

External Clock Rise Time (EXTAL)

EXf

External Clock Fall Time (EXTAL)

RESET Rise Time

RESET Fall Time

Input Rise Time (except EXTAL,

RESET)

100

Table 8. Z80180-8 AC Characteristics (continued)

No. Symbol Item

Z80180-8

Unit

Min.

Max.

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

Input Fall Time (except EXTAL,

RESET)

100

Table 9. Z80180-10 AC Characteristics

No. Symbol Item

Z80180-10

Unit

Min.

Max.

cyc

Clock Cycle Time

100

2000 ns

CHW

Clock

H Pulse Width

CLW

Clock

L Pulse Width

Clock Fall Time

Clock Rise Time

ØRise to Address Valid Delay

Address Valid to MREQ Fall or IORQ

Fall)

MED1

Ø Fall to MREQ Fall

Delay

RDD1

Ø Fall to

RD Fall

Delay

IOC = 1

Ø Rise to

RD Rise

Delay

IOC = 0

M1D1

Ø Rise to

M1 Fall

Delay

Address Hold Time from
(MREQ,

IOREQ, RD, WR)

MED2

Ø Fall to MREQ Rise

Delay

RDD2

Ø Fall to

RD Rise

Delay

Table 8. Z80180-8 AC Characteristics (continued)

No. Symbol Item

Z80180-8

Unit

Min.

Max.

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

M1D2

Ø Rise to

M1 Rise

Delay

DRS

Data Read Set-up Time

DRH

Data Read Hold Time

STD1

Ø Fall to ST Fall

Delay

STD2

Ø Fall to ST Rise

Delay

WAIT Set-up Time to Ø Fall

WAIT Hold Time from Ø Fall

WDZ

Ø Rise to Data Float Delay

WRD1

Ø Rise to

WR Fall

Delay

WDD

Ø Fall to

WRITE Data Delay Time

WDS

WRITE Data Set-up Time to WR Fall

WRD2

Ø Fall to

WR Rise

Delay

WRP

WR Pulse Width

110

26a

WR Pulse Width (I/O WRITE Cycle)

210

WDH

WRITE Data Hold Time from (WR Rise

)

IOD1

Ø Fall to

IORQ Fall

Delay

IOC = 1

Ø Rise to

IORQ Fall

Delay

IOC = 1

IOD2

Ø Fall to

IORQ Rise

Delay

IOD3

M1 Fall to IORQFall

Delay

200

INTS

INT Set-up Time to Ø Fall

INTS

INT Hold Time from Ø Fall

Table 9. Z80180-10 AC Characteristics (continued)

No. Symbol Item

Z80180-10

Unit

Min.

Max.

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

NMIW

NMI Pulse Width

BRS

BUSREQ Set-up Time to Ø Fall

BRH

BUSREQ Hold Time from Ø Fall

BAD1

Ø Rise to

BUSACK Fall

Delay

BAD2

Ø Fall to

BUSACK Rise

Delay

BZD

Ø Rise to Bus Floating Delay Time

MEWH

MREQ Pulse Width (High)

MEWL

MREQ Pulse Width (Low)

RFD1

Ø Rise to

RFSH Fall Delay

RFD2

Ø Rise to

RFSHRise Delay

HAD1

Ø Rise to

HALT Fall Delay

HAD2

Ø Rise to

HALTRise Delay

DRQS

/DREQi Set-up Time to Ø Rise

DRQH

/DREQi Hold Time from Ø Rise

TED1

Ø Fall to

TENDi Fall Delay

TED2

Ø Fall to

TENDiRise Delay

ED1

Ø Rise to E Rise Delay

ED2

Ø Fall or Rise to E Fall Delay

WEH

E Pulse Width (High)

WEL

E Pulse Width (Low)

110

Enable Rise Time

Table 9. Z80180-10 AC Characteristics (continued)

No. Symbol Item

Z80180-10

Unit

Min.

Max.

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

Enable Fall Time

TOD

Ø Fall to Timer Output Delay

150

STDI

CSIO Transmit Data Delay Time (Internal Clock
Operation)

150

STDE

CSIO Transmit Data Delay Time (External Clock
Operation)

7.5tcy
c
+150

SRSI

CSIO Receive Data Set-up Time (Internal Clock
Operation)

tcyc

SRHI

CSIO Receive Data Hold Time (Internal Clock
Operation)

tcyc

SRSE

CSIO Receive Data Set-up Time (External Clock
Operation)

tcyc

SRHE

CSIO Receive Data Hold Time (External Clock
Operation)

tcyc

RES

RESET Set-up Time to Ø Fall

REH

RESET Hold Time from Ø Fall

OSC

Oscillator Stabilization Time

TBD

EXr

External Clock Rise Time (EXTAL)

EXf

External Clock Fall Time (EXTAL)

RESET Rise Time

RESET Fall Time

Input Rise Time (except EXTAL,

RESET)

100

Table 9. Z80180-10 AC Characteristics (continued)

No. Symbol Item

Z80180-10

Unit

Min.

Max.

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

Figure 16. CPU Timing (Op Code Fetch, I/O WRITE, and I/O READ

Cycles)

PHI

ADDRESS

WAIT

MREQ

IORQ

Data IN

Data OUT

RESET

Opcode Fetch Cycle

I/O Write Cycle*

I/O Read Cycle*

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

DMA Control Signals

Notes:

1. t

DRQS

and t

DHQH

are specified for the rising edge of clock followed by T

2. t

DRQS

and t

DHQH

are specified for the rising edge of clock.

3. DMA cycle starts.
4. CPU cycle starts.

Figure 19. DMA Control Signals

(at level sense)

DREQi

(at level sense)

TENDi

*3 17

DREQi

CPU or DMA READ/WRITE Cycle (Only DMA WRITE Cycle for TENDi)

46*1

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

DMA Contrl Signals

Figure 20. E Clock Timing (Memory R/W Cycle, I/O R/W Cycle)

Figure 21. E Clock Timing (Bus Release, Sleep, System Stop Modes

E Clock Timing (Memory READ/WRITE Cycle, I/O READ/WRITE Cycle)

(Memory READ/WRITE)

(I/O READ)

(I/O WRITE)

~~
~~

PH1ø

E
BUS RELEASE mode
SLEEP mode
SYSTEM STOP mode

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

Figure 25. CSIO Receive/Transmit Timing

CSIO Receive/Transmit Timing

Rise Time and Fall Times

11.5t

cyc

Transmit data

11.5t

cyc

11t

cyc

16.5t

cyc

11t

cyc

16.5t

cyc

(External Clock)

Transmit data

(Internal Clock)

Receive data

(External Clock)

Receive data

(Internal Clock)

CSIO CLock

IL1

IH1

EXTAL V

IL1

IH1

Input
Rise Time

Exter-
nal

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

Figure 26. Rise Time and Fall Times

ASCI Register Description

Figure 27. ASCI Block Diagram

ASCI Block Diagram

Internal Address/Data Bus

ASCI Transmit Data Register

Ch 0: TDR0

ASCI Transmit Shift Register*

Ch 0: TSR0

ASCI Receive Data FIFO

Ch 0: RDR0

ASCI Receive Shift Register*

Ch 0: RSR0 (8)

ASCI Control Register A

Ch 0: CNTLA0 (8)

ASCI Control Register B

Ch 0: CNTB0 (8)

ASCI Status Register

Ch 0: STAT0 (8)

ASCI Status FIFO

Ch 0

ASCI Transmit Data Register

Ch 1: TDR1

ASCI Transmit Shift Register*

Ch 1: TSR1

ASCI Receive Data FIFO

Ch 1: RDR1

ASCI Receive Shift Register*

Ch 1: RSR1 (8)

ASCI Control Register A

Ch 1: CNTLA1 (8)

ASCI Control Register B

Ch 1: CNTB1 (8)

ASCI Status Register

Ch 1: STAT1 (8)

ASCI Status FIFO

Ch 1

TXA

RXA

RTS

CTS

DCD

TXA

RXA

CTS

ASCI

Control

Baud Rate

Generator 0

Baud Rate

Generator 1

CKA

Note: *Not Program

Interrupt Request

Accessible.

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

ASCI Register Description

The following paragraphs explain the various functions of the ASCI
registers.

ASCI Transmit Shift Register 0 (TSR0, TSR1). When the ASCI
Transmit Shift Register (

TSR

) receives data from the ASCI Trans-

mit Data Register (

TDR

), the data is shifted out to the

TxA

pin.

When transmission is completed, the next byte (if available) is
automatically loaded from

TDR

into

TSR

and the next transmission

starts. If no data is available for transmission,

TSR

IDLE

s by output-

ting a continuous High level. This register is not program accessi-
ble

ASCI Transmit Data Register 0,1 (TDR0, TDR1). I/O address =

06h

07h

. Data written to the ASCI Transmit Data Register is trans-

ferred to the

TSR

as soon as

TSR

is empty. Data can be written

while

TSR

is shifting out the previous byte of data. The ASCI trans-

mitter is double buffered.

Data can be written into and read from the ASCI Transmit Data
Register. If data is read from the ASCI Transmit Data Register, the
ASCI data transmit operation is not affected by this

READ

opera-

tion.

ASCI Transmit Data Registers

06h

and

07h

hold the ASCI transmit data for

channel 0 and channel 1, respectively.

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

ASCI Receive Shift Register 0,1 (RSR0, RSR1)

This register

receives data shifted in on the

RxA

pin. When full, data is automati-

cally transferred to the ASCI Receive Data Register (

RDR

) if it is

empty. If

RSR

is not empty when the next incoming data byte is

shifted in, an overrun error occurs. This register is not program
accessible.

ASCI Receive Data FIFO 0,1 (RDR0, RDR1)

I/O Address =

08h

09h

The ASCI Receive Data Register is a

READ-ONLY

complete incoming data byte is assembled in

RSR

, it is automati-

cally transferred to the 4 character Receive Data First-In First-Out
(FIFO) memory. The oldest character in the FIFO (if any) can be
read from the Receive Data Register (

RDR

). The next incoming

data byte can be shifted into

RSR

while the FIFO is full. The ASCI

receiver is well buffered.

ASCI Receive Register

08h

and

09h

hold the ASCI receive data for

channel 0 and channel 1, respectively.

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

ASCI Channel Control Register A

Figure 32. ASCI Channel Control Register A

MPE: Multi-Processor Mode Enable (bit 7)

. The ASCI features a

multiprocessor communication mode that utilizes an extra data bit
for selective communication when a number of processors share a
common serial bus. Multiprocessor data format is selected when
the

bit in

CNTLB

is set to

. If multiprocessor mode is not

selected (

bit in

CNTLB = 0

MPE

exhibits no effect. If multipro-

cessor mode is selected,

MPE

enables or disables the wake-up

feature as follows. If

MBE

is set to

, only received bytes in which

the

MPB

(multiprocessor bit) =

can affect the

RDRF

and error

flags. Effectively, other bytes (with

MPB = 0

) are ignored by the

ASCI

. If

MPE

is reset to

, all bytes, regardless of the state of the

ASCI Channel Control Register A

Bit

MPE

R/W

RTS0

MPBR/

MOD2

MOD1

MOD0

R/W

ASCI Control Register A 0 (CNTLA0: I/O Address = 00h)

R/W

EFR

Bit

MPE

R/W

MOD2

MOD1

MOD0

R/W

ASCI Control Register A 1 (CNTLA1: I/O Address = 01h)

R/W

MPBR/

EFR

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

MPB

data bit, affect the

REDR

and error flags.

MPE

is cleared to

during

RESET

RE: Receiver Enable (bit 6).

When

is set to

, the ASCI transmit-

ter is enabled. When

is reset to

, the transmitter is disables and

any transmit operation in progress is interrupted. However, the

TDRE

flag is not reset and the previous contents of

TDRE

are held.

is cleared to

IOSTOP

mode during

RESET

TE: Transmitter Enable (bit 5).

When

is set to

, the ASCI

receiver is enabled. When

is reset to

, the transmitter is dis-

abled and any transmit operation in progress is interrupted. How-
ever, the

TDRE

flag is not reset and the previous contents of

TDRE

are held.

is cleared to

IOSTOP

mode during

RESET

RTS0: Request to Send Channel 0 (bit 4 in CNTLA0 only).

If bit

the System Configuration Register is

, the

RTS0/TxS

pin features

the

RTS0

function.

RTS0

allows the ASCI to control (

START/STOP

)

another communication devices transmission (for example, by con-
necting to that device's

CTS

input).

RTS0

is essentially a

bit out-

put port, having no side effects on other ASCI registers or flags. Bit

CNTLA1

is not used.

MPBR/EFR: Multiprocessor Bit Receive/Error Flag Reset (bit 3)

When multiprocessor mode is enabled (

CNTLB = 1

MPBR

when read, contains the value of the

MPB

bit for the most recent

receive operation. When written to

, the

EFR

function is selected

to reset all error flags (

OVRN

and

BRK

in the

ASEXT

regis-

ter) to

MPBR/EFR

is undefined during

RESET

MOD2, 1, 0: ASCI Data Format Mode 2, 1, 0 (bits 20).

These bits

program the ASCI data format as shown in Table 8.

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

The data formats available based on all combinations of

MOD2

MOD1

, and

MOD0

are indicated in Table 9, Data Formats.

Table 10. ASCI Data Formats Mode 2, 1, 0

Bit

Description

MOD2 = 0

®7 bit data

MOD2 = 1

®8 bit data

MOD1 = 0

®No parity

MOD1 = 1

®Parity enabled

MOD0 = 0

®1 stop bit

MOD0 = 1

®2 stop bits

Table 11. Data Formats

MOD2 MOD1

MOD0

Data Format

Start + 7 bit data + 1 stop

Start + 7 bit data + 2 stop

Start + 7 bit data + parity + 1 stop

Start + 7 bit data + parity + 2 stop

Start + 8 bit data + 1 stop

Start + 8 bit data + 2 stop

Start + 8 bit data + parity + 1 stop

Start + 8 bit data + parity + 2 stop

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

ASCI CHANNEL CONTROL REGISTER B

Figure 33. ASCI Channel Control Register B

MPBT: Multiprocessor Bit Transmit (bit 7)

. When multiprocessor

communication format is selected (

bit =

MPBT

is used to

specify the

MPB

data bit for transmission. If

MPBT = 1

, then

MPB = 1

is transmitted. If

MPBT = 0

, then

MPB = 0

is transmitted.

MPBT

state

is undefined during and after

RESET

MP: Multiprocessor Mode (bit 6)

. When

is set to

, the data for-

mat is configured for multiprocessor mode based on the

MOD2

(number of data bits) and

MOD0

(number of stop bits) bits in

CNTLA

. The format is as follows.

Start bit + 7 or 8 data bits + MPB bit + 1 or 2 stop bits

Multiprocessor (

MP=1

) format does not feature any provision for

parity.

MP = 0

, the data format is based on

MOD0

MOD1

MOD2

, and

may include parity. The

bit is cleared to

during

RESET

ASCI Channel Control Register B

Bit

MPBT

R/W

CTS/

PEO

SS2

SS1

SS0

R/W

ASCI Control Register B 1 (CNTLB1: I/O Address = 03h)

R/W

ASCI Control Register B 0 (CNTLB0: I/O Address = 02h)

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

CTS/PS: Clear to Send/Prescale (bit 5). f bit

of the System

Configuration Register is

, the

CTS0

RxS

pin features the

CTS0

function, and the state of the pin can be read in bit

CNTLB0

in a

real-time, positive-logic fashion (

HIGH = 1

LOW

= 0). If bit

in the

System Configuration Register is

to auto-enable

CTS0

, and the

pin is negated (High), the

TDRE

bit is inhibited (forced to

). Bit

CNTLB1

reads back as

If the

SS20

bits in this register are not

111

, and the

BRG

mode bit

in the

ASEXT

, then writing to this bit sets the prescale

(PS) control. Under these circumstances, a

indicates a divide-by-

10 prescale function, while a

indicates divide-by-30. The bit

resets to

PEO: Parity Even Odd (bit 4).

PEO

selects oven or odd parity.

PEO

does not affect the enabling/disabling of parity (

MOD1

bit of

CNTLA

). If

PEO

is cleared to

, even parity is selected. If

PEO

is set

, odd parity is selected.

PEO

is cleared to

during

RESET

DR: Divide Ratio (bit 3). If the

bit in the

ASEXT

, this

bit specifies the divider used to obtain baud rate from the data sam-
pling clock. If

is reset to

, divide- by-16 is used, while if

set to

, divide-by-64 is used.

is cleared to

during

RESET

SS2,1,0: Source/Speed Select 2,1,0 (bits 20). If these bits are

111

, as they are after

RESET

, the

CKA

pin is used as a clock input,

and is divided by 1, 16, or 64 depending on the

bit and the

bit in the

ASEXT

If these bits are not

111

and the

BRG

mode bit is

ASEXT

, these

bits specify a power-of-two divider for the

PHI

clock as indicated in

Divide Ratio.

Setting or leaving these bits as

111

makes sense for a channel only

when its

CKA

pin is selected for the

CKA

function.

CKAO/CKS

fea-

tures the

CKAO

function when bit

of the System Configuration

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

DCD0/CKA1

features the

CKA1

function when bit

the Interrupt Edge register is

ASCI Status Register 0, 1 (STAT0, 1)

Each channel status register allows interrogation of ASCI commu-
nication, error and modem control signal status, and enabling or
disabling of ASCI interrupts.

Table 12. Divide Ratio

SS2

SS1

SS0

Divide Ratio

¸1

¸2

¸4

¸8

¸16

¸32

¸64

External Clock

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

Figure 34. ASCI Status Registers

RDRF: Receive Data Register Full (bit 7).

RDRF

is set to

when

an incoming data byte is loaded into an empty

RxFIFO

If a framing or parity error occurs,

RDRF

is still

set and the receive data (which generated the
error) is still loaded into the FIFO.

RDRF

is cleared to

by reading

RDR

and most recent character in

the FIFO from

IOSTOP

mode, during

RESET

and for ASCI0 if the

DCD0

input is auto-enabled and is negated (High).

OVRN: Overrun Error (bit 6). An overrun condition occurs when
the receiver finishes assembling a character, but the

RxFIFO

is full

so that there is no room for the character. However, this status bit is
not set until the most recent character received before the overrun
becomes the oldest byte in the FIFO. This bit is cleared when soft-
ware writes a

to the

EFR

bit in the

CNTLA

ASCI Status Registers

Bit

RDRF

OVRN

R/W

DCD

TDRE

TIE

ASCI Status Register 0 (STAT0: I/O Address = 04h)

R/W

Bit

RDRF

OVRN

R/W

TDRE

TIE

ASCI Status Register 1 (STAT1: I/O Address = 05h)

R/W

Note:

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

RESET

, in

IOSTOP

mode, and for ASCI0 if the

DCD0

pin is auto

enabled and is negated (High).

When an overrun occurs, the receiver does not place the character
in the shift register into the FIFO, nor any subsequent characters,
until the last good character comes to the top of the FIFO so that

OVRN

is set, and software then writes a

EFR

to clear it.

PE: Parity Error (bit 5). A parity error is detected when parity
checking is enabled by the

MOD1

bit in the

CNT1LA

, and a character is assembled in which the parity does not match

the

PEO

bit in the

CNTLB

until or unless the error character becomes the oldest one in the

RxFIFO

is cleared when software writes a

to the

EFR

bit in the

CNTRLA

RESET

, in

IOSTOP

mode, and for

ASCI0 if the

DCD0

pin is auto-enabled and is negated (High).

FE: Framing Error (bit 4). A framing error is detected when the
stop bit of a character is sampled as

0/SPACE

. However, this status

bit is not set until or unless the error character becomes the oldest
one in the

RxFIFO

is cleared when software writes a

to the

EFR

bit in the

CNTLA

RESET

, in

IOSTOP

mode,

and for ASCIO if the

DCDO

pin is auto-enabled and is negated

(High).

REI: Receive Interrupt Enable (bit 3).

RIE

should be set to

enable ASCI receive interrupt requests. When

RIE

, the receiver

requests an interrupt when a character is received and

RDRF

set, but only if neither DMA channel sets its request-routing field to
receive data from this ASCI. That is, if

SM10

are

and

SAR1716

are

, or

DIM1

and

IAR1716

are

, then ASCI1 does not

request an interrupt for

RDRF

. If

RIE

, either ASCI requests an

interrupt when

OVRN

is set, and ASCI0 requests an inter-

rupt when

DCD0

goes High.

RIE

is cleared to

RESET

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

DCD0: Data Carrier Detect (bit 2 STAT0). If bit

of the Interrupt

Edge Register (

IER0

) is

, the

DCD0/CKA1

pin features the

DCD0

function, and this bit is set to

when the pin is High. It is cleared to

on the first

READ

STAT0

following the pin's transition from High

to Low and during

RESET

. When

IER0

, bit

of the

ASEXT0

reg-

ister is

to select auto-enabling, and the pin is negated (High), the

bit 2 of

STAT1

is not used.

TDRE: Transmit Data Register Empty (bit 1).

TDRE = 1

indicates

that the

TDR

is empty and the next transmit data byte is written to

TDR

. After the byte is written to

TDR

TDRE

is cleared to

until the

ASCI transfers the byte from

TDR

to the

TSR

and then

TDRE

again set to

TDRE

is set to

IOSTOP

mode and during

RESET

On ASCIO, if the

CTS0

pin is auto-enabled in the

ASEXT0

registers

and the pin is High,

TDRE

is reset to

TIE: Transmit Interrupt Enable (bit 0).

TIE

should be set to

enable ASCI transmit interrupt requests. If

TIE = 1

, an interrupt is

requested when

TDRE = 1

TIE

is cleared to

during

RESET

CSIO Control/Status Register

CNTR: I/O Address = 0Ah.

CNTR

is used to monitor

CSIO

status,

enable and disable the

CSIO

, enable and disable interrupt genera-

tion, and select the data clock speed and source.

Figure 35. CSIO Control Register

CSIO Control Register

Bit

EIE

R/W

SS2

SS1

SS0

R/W

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

EF: End Flag (bit 7).

is set to

by the

CSIO

to indicate comple-

tion of an 8-bit data transmit or receive operation. If the End Inter-
rupt Enable (

EIE

) bit =

when

is set to

, a CPU interrupt

request is generated. Program access of

TRDR

only occurs if

EF =

. The

CSIO

clears

when

TRDR

is read or written.

cleared to

during

RESET

and

IOSTOP

mode.

EIE: End Interrupt Enable (bit 6).

EIE

is set to

to generate a

CPU interrupt request. The interrupt request is inhibited if

EIE

reset to

EIE

is cleared to

during

RESET

RE: Receive Enable (bit 5). A

CSIO

receive operation is started by

setting

. When

is set to

, the data clock is enabled. In

internal clock mode, the data clock is output from the

CKS

pin. In

external clock mode, the clock is input on the

CKS

pin. In either

case, data is shifted in on the

RXS

pin in synchronization with the

(internal or external) data clock. After receiving 8 bits of data, the

CSIO

automatically clears

is set to

, and an interrupt (if

enabled by

EIE = 1

) is generated.

and

are never both set to 1

at the same time.

is cleared to 0 during

RESET

and ISTOP

mode.

Transmit Enable (bit 4). A

CSIO

transmit operation is started by

setting

to 1. When

is set to 1, the data clock is enabled.

When in internal clock mode, the data clock is output from the

CKS

pin. In external clock mode, the clock is input on the

CKS

pin. In

either case, data is shifted out on the TXS pin synchronous with the
(internal or external) data clock. After transmitting 8 bits of data, the

CSIO

automatically clears

to 0,

is set to

, and an interrupt (if

enabled by

EIE = 1

) is generated.

and

are never both set to 1

at the same time.

is cleared to 0 during

RESET

and

IOSTOP

mode.

SS2, 1, 0: Speed Select 2, 1, 0 (bits 2-0).

SS2

SS1

and

SS0

select

the

CSIO

transmit/receive clock source and speed.

SS2

SS1

and

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

SS0

are all set to

during

RESET

. Table 13 shows

CSIO

Baud Rate

Selection.

After

RESET

, the

CKS

pin is configured as an external clock input

(

SS2

SS1

SS0 = 1

). Changing these values causes

CKS

to become

an output pin and the selected clock is output when transmit or
receive operations are enabled.

Table 13. CSIO Baud Rate Selection

SS2

SS1

SS0

Divide Ratio

¸20

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¸640

¸1280

External Clock
Input(less than

¸20)

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

CSIO Transmit/Receive Data Register

(

TRDR

: I/O Address = 0Bh)

Figure 36. ASCI Receive Register Channel 1R

Timer Data Register Channel 0L

TMDR0L: OCH

0Ch

Figure 37. ASCI Receive Register Channel 1R

ASCI Receive Register Channel 1R

CSIO Transmit/Receive Data

Timer Data

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

Timer Reload Register 0H

RLDR0H

0Fh

Figure 40. Timer Reload Register

Timer Control Register (TCR)

TCR

monitors both channels (

PRT0

PRT1

)

TMDR

status. It also

controls enabling and disabling of down counting and interrupts
along with controlling output pin

A18

OUT

for

PRT1

Figure 41. Timer Control Register (TCR: I/O Address = 10h)

Timer Reload Register

Timer Control Register (TCR: I/O Address = 10h)

Timer Reload Data

Bit

TIF1

TIF0

R/W

TIE1

TIE0

TOC0

TDE1

TDE0

R/W

TOC1

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

TIF1: Timer Interrupt Flag 1 (bit 7). When

TMDR1

decrements to

TIF1

is set to

, and, when enabled by

TIE1 = 1

, an interrupt

request is generated.

TIF1

is reset to

when

TCR

is read and the

higher or lower byte of

TMDR1

is read. During

RESET

TIF1

cleared to

TIF0: Timer Interrupt Flag 0 (bit 6). When

TMDR0

decrements to

TIF0

is set to

, and, when enabled by

TIE0 = 1

, an interrupt

request is generated

TIF0

is reset to

when

TCR

is read and the

higher or lower byte of

TMDR0

is read. During

RESET

TIF0

cleared to

TIE1: Timer Interrupt Enable 1 (bit 5). When

TIE0

is set to

TIF1

= 1

generates a CPU interrupt request. When

TIE0

is reset to

, the

interrupt request is inhibited. During

RESET

TIE0

is cleared to

TOC1, 0: Timer Output Control (bits 3, 2).

TOC1

and

TOC0

con-

trol the output of

PRT1

using the multiplexed

OUT

DREQ

pin as

indicated in Timer Output Control. During

RESET

TOC1

and

TOC0

are cleared to

. If bit

of the

IAR1B

, the

OUT

function

is selected. By programming

TOC1

and

TOC0

, the

OUT

DREQ

can be forced High, Low, or toggled when

TMDR1

decrements to

TDE1, 0: Timer Down Count Enable (bits 1, 0).

TDE1

and

TDE0

enable and disable down counting for

TMDR1

and

TMDR0

, respec-

tively. When

TDEn

(

N = 0,1

) is set to

, down counting is stopped

Table 14. Timer Output Control

TOC1

TOC0

Output

Inhibited The T

OUT

/DREQ pin is not affected by

the PRT.

Toggled

If bit 3 of IAR1B is 1, the T

OUT

/DREQ pin

toggles or is set Low or High as indicated.

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

and

TMDRn

is freely read or written.

TDE1

and

TDE0

are cleared to

during

RESET

and

TMDRn

do not decrement until

TDEn

is set to

ASCI Extension Control Register Channels 0 and 1

ASEXT0 and ASEXT1

The ASCI Extension Control Register controls functions newly
added to the ASCIs in the Z80180 family.

All bits in this register reset to 0.

Figure 42. ASCI Extension Control Registers, Channel 0 and 1

DCD0 dis (bit 6, ASCI0 only). If bit

of the Interrupt Edge Regis-

ter is

to select the

DCD0

function for the

DCD0

CKA1

pin, and this

bit is

, the

DCD0

pin auto-enables the

ASCI0

receiver. When the

pin is negated/High, the Receiver is held in a

RESET

state. If bit

ASCI Extension Control Registers, Channel 0 and 1

Note:

Bit

DCDO

BRGO

Break

Send

ASCI Extension Control Register 0(ASEXT0 I/O Address = 12h)

CTSO

Mode

Nab

Break

Bit

BRGI

Break

Send

Mode

Enab

Break

ASCI Extension Control Register 1 (ASEXT1 I/O Address = 13h)

Reserved

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

the

IER

and this bit is

, the state of the

DCD

-pin has no effect

on receiver operation. In either state of this bit, software can read
the state of the

DCD0

pin in the

STAT0

interrupts on a rising edge of

DCD0

CTS0 dis (bit 5, ASCI0 only). If bit

of the System Configuration

to select the

CTS0

function of the

CTS0

RXS

pin, and

this bit is

, then the

CTS0

pin auto-enables the

ASCIO

transmitter,

in that when the pin is negated (High), the

TDRE

bit in the

STAT0

. If bit

of the System Configuration Register

and this bit is

, the state of the

CTS0

pin exhibits no effect on

the transmitter. Regardless of the state of this bit, software can
read the state of the

CTS0

pin the

CNTLB0

X1 (bit 4). If this bit is

, the clock from the Baud Rate Generator or

CKA

pin is received as a 1X bit clock (sometimes called isochro-

nous mode). In this mode, receive data on the

RXA

pin must be

synchronized to the clock on the

CKA

pin, regardless of whether

CKA

is an input or an output. If this bit is

, the clock from the Baud

Rate Generator or

CKA

pin is divided by 16 or 64 per the

bit in

CNTLB

data on the

RXA

pin is not required to be synchronized to a clock.

BRG Mode (bit 3). If the

SS20

bits in the

CNTLB

111

, and this bit is

, the ASCI Baud Rate Generator divides

PHI

10 or 30, depending on the

bit in

CNTLB

, and then by a power

of two selected by the

SS20

bits, to obtain the clock that is pre-

sented to the transmitter and receiver and that can be output on
the

CKA

pin. If

SS20

are not

111

, and this bit is

, the Baud Rate

Generator divides

PHI

by twice (the 16-bit value programmed into

the Time Constant Registers, plus 2). This mode is identical to the
operation of the baud rate generator in the ESCC.

Break Enable (bit 2). If this bit is

, the receiver detects break con-

ditions and report them in bit

, and the transmitter sends breaks

under the control of bit

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

Break Detect (bit 1). The receiver sets this

READ-ONLY

bit to

when an all-zero character with a Framing Error becomes the old-
est character in the

RxFIFO

. The bit is cleared when software writes

to the

EFR

bit in

CNTLA

RESET

, by

IOSTOP

mode, and for

ASCIO

if the

DCD0

pin is auto-enabled and is

negated (High).

Send Break (bit 0). If this bit and bit

are both

, the transmitter

holds the

TXA

pin Low to send a break condition. The duration of

the break is under software control (one of the

PRTs

CTCs

can

be used to time it). This bit resets to

, in which state

TXA

carries

the serial output of the transmitter.

Timer Data Register Channel 1L

Mnemonic TMDR1L:14H

Address 14

Figure 43. Timer Data Register

Timer Data Register

Timer Data

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

anteed. In IOSTOP mode, the free running counter continues
counting down. It is initialized to

FFH

,during RESET.

Figure 47. Timer Data Register

DMA Source Address Register Channel 0

(

SAR0: I/O ADDRESS = 20h to 22h

) specifies the physical source

address for channel 0 transfers. The register contains 20 bits and
can specify up to 1024-KB memory addresses or up to 64-KB I/O
addresses. Channel 0 source can be memory, I/O, or memory
mapped I/O. For I/O, the MS bits of this register identify the

REQUEST HANDSHAKE

signal.

Timer Data Register

Counting Data

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

DMA Source Address Register, Channel 0L

Mnemonic SAR0L

Address 20

Figure 48. DMA Channel 0L

DMA Source Address Register, Channel 0H

Mnemonic SAR0H

Address 21

Figure 49. DMA Channel 0H

Timer Data Register

DMA Channel 0 Address

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

DMA Source Address Register Channel 0B

Mnemonics SAR0B

Address 22

Figure 50. DMA Channel 0B

DMA Destination Address Register Channel 0

(

DAR0: I/O ADDRESS = 23h to 25h

) specifies the physical destination

address for channel 0 transfers. The register contains 20 bits and
can specify up to 1024-KB memory addresses or up to 64-KB I/O
addresses. Channel 0 destination can be memory, I/O, or memory
mapped I/O. For I/O, the MS bits of this register identify the

REQUEST HANDSHAKE

signal for channel 0.

Timer Data Register

DMA Channel B Address

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

DMA Destination Address Register Channel 0B

Mnemonic DAR0B

Address 25

Figure 53. DMA Destination Address Register Channel 0B

In the

and Z Mask, these DMA registers are

expanded from 4 bits to 3 bits in the package
version of CP-68.

DMA Byte Count Register Channel 0

(

BCRO: I/O ADDRESS = 26h to 27h

) specifies the number of bytes to

be transferred. This register contains 16 bits and may specify up to
64-KB transfers. When one byte is transferred, the register is dec-
remented by 1. If n bytes should be transferred, n must be stored
before the DMA operation.

DMA Destination Address Register Channel 0B

Table 15. DMA Transfer Requests

A19*

A18

A17

A16

DMA Transfer Request

DREQ0

TDR0 (ASCI0)

TDR1 (ASCI1)

Not Used

Note:

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

DMA Byte Count Register Channel 1L

Mnemonic BCR1L

Address 2E

Figure 56. DMA Byte Count Register 1L

DMA Byte Count Register Channel 0H

Mnemonic BCR1H

Address 2F

Figure 57. DMA Byte Count Register 0H

DMA Memory Address Register Channel 1

(

MAR1: I/O ADDRESS = 28h to 2Ah

) specifies the physical memory

address for channel 1 transfers, which may also be a destination or

DMA Byte Count Register 1L

DMA Byte Count Register 0H

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

source memory address. The register contains 20 bits and may
specify up to 1024-KB memory address.

DMA Memory Address Register, Channel 1L

Mnemonic MAR1L

Address 28

Figure 58. DMA Memory Address Register, Channel 1L

DMA Memory Address Register, Channel 1H

Mnemonic MAR1H

Address 29DMA Memory Address Register, Channel 1B

Figure 59. DMA Memory Address Register, Channel 1H

Mnemonic MAR1B

DMA Memory Address Register, Channel 1L

DMA Memory Address Register, Channel 1H

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

Address 2A

Figure 60. DMA Memory Address Register, Channel 1B

DMA I/O Address Register Channel 1

(

IAR1: I/O ADDRESS = 2Bh to 2Dh

) specifies the I/O address for

channel 1 transfers, which may also be a destination or source I/O
address. The register contains 16 bits of I/O address; its most sig-
nificant byte identifies the

REQUEST HANDSHAKE

signal and con-

trols the Alternating Channel feature.

All bits in

IAR1B

reset to

Figure 61. IAR MS Byte Register (IARIB: I/O Address 2Dh

DMA Mem

ory Address Register, Channel 1B

IAR MS Byte Register (IARIB: I/O Address 2Dh)

Bit

A/T

OUT

DREQ

Req 1 Sel

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

DMA I/O Address Register Channel 1B

Mnemonic IAR1B

Address 2D

Figure 64. DMA I/O Address Register Channel 1B

DMA Status Register (DSTAT)

DSTAT

is used to enable and disable DMA transfer and DMA termi-

nation interrupts.

DSTAT

also indicates DMA transfer status, in

other words, completed or in progress.

Mnemonic DSTAT

Address 30

Figure 65. DMA Status Register (DSTAT: I/O Address = 30h)

DMA I/O Address Register Channel 1B

DMA Status Register (DSTAT: I/O Address = 30h)

Bit

DE1

DE0

DWE1

R/W

DWE0

DIE1

DIE0

DME

R/W

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

DE1: DMA Enable Channel 1 (bit 7). When

DE1 = 1

and

DME = 1

channel 1 DMA is enabled. When a DMA transfer terminates
(

BCR1 = 0

DE1

is reset to

by the DMAC. When

DE1 = 0

and the

DMA interrupt is enabled (

DIE1 = 1

), a DMA interrupt request is

made to the CPU.

To perform a software

WRITE

DE1

DWE1

should be written with

during the same register

WRITE

access. Writing

DE1

disables

channel 1 DMA, but DMA is restartable. Writing

DE1

enables

channel 1 DMA and automatically sets

DME

(DMA Main Enable) to

DE1

is cleared to

during

RESET

DE0: DMA Enable Channel 0 (bit 6). When

DE0 = 1

and

DME = 1

channel 0 DMA is enabled. When a DMA transfer terminates
(

BCR0 = 0

DE0

is reset to

by the DMAC. When

DE0 = 0

and the

DMA interrupt is enabled (

DIE0 = 1

), a DMA interrupt request is

made to the CPU.

To perform a software

WRITE

DE0

DWE0

should be written with

during the same register

WRITE

access. Writing

DE0

disables

channel 0 DMA. Writing

DE0

enables channel 0 DMA and

automatically sets

DME

(DMA Main Enable) to

DE0

is cleared to

during

RESET

DWE1: DE1 Bit WRITE Enable (bit 5). When performing any soft-
ware

WRITE

DE1

DWE1

should be written with

during the

same access.

DWE1

always reads as

DWE0: DE0 Bit WRITE Enable (bit 4). When performing any soft-
ware

WRITE

DE0

DWE0

should be written with

during the

same access.

DWE0

always reads as

DIE1: DMA Interrupt Enable Channel 1 (bit 3). When

DIE0

is set

, the termination channel 1 DMA transfer (indicated when

DE1 =

) causes a CPU interrupt request to be generated. When

DIE0 = 0

the channel 0 DMA termination interrupt is disabled.

DIE0

cleared to

during

RESET

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

DIE0: DMA Interrupt Enable Channel 0 (bit 2). When

DIE0

is set

, the termination channel 0 of DMA transfer (indicated when

DE0 = 0

) causes a CPU interrupt request to be generated. When

DIE0 = 0

, the channel 0 DMA termination interrupt is disabled.

DIE0

is cleared to

during

RESET

DME: DMA Main Enable (bit 0). A DMA operation is only enabled
when its

bit (

DE0

for channel 0,

DE1

for channel 1) and the

DME

bit is set to

When

NMI

occurs,

DME

is reset to

, disabling DMA activity during

the

NMI

interrupt service routine. To restart DMA,

and/or

DE1

should be written with a

(even if the contents are already

). This

WRITE

automatically sets

DME

, allowing DMA operations to

continue.

DME

cannot be directly written. It is cleared to

NMI

or indirectly set to

by setting

DE0

and/or

DE1

DME

is cleared to

during

RESET

DMA Mode Register (DMODE)

DMODE

is used to set the addressing and transfer mode for chan-

nel 0.

Note:

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

Mnemonic DMODE

Address 31h

Figure 66. DMA Mode Register (DMODE: I/O Address = 31h)

DM1, DM0: Destination Mode Channel 0 (bits 5,4). Specifies
whether the destination for channel 0 transfers is memory or I/O,
and whether the address should be incremented or decremented
for each byte transferred.

DM1

and

DM0

are cleared to

during

RESET

. See Table 16.

SM1, SM0: Source Mode Channel 0 (bits 3, 2). Specifies whether
the source for channel 0 transfers is memory or I/O, and whether

DMA Mode Register (DMODE: I/O Address = 31h)

Table 16. Channel 0 Destination

DM1

DM0

Memory I/O

Memory Increment/Decrement

Memory

fixed

I/O

fixed

Bit

DM1

DM0

R/W

SM1

SM0

MMOD

R/W

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

the address should be incremented or decremented for each byte
transferred. See Table 17.

Channel 1 Transfer Mode describes all DMA transfer mode combi-
nations of

DM0

DM1

SM0

, and

SM1

. Because I/O to/from I/O trans-

fers are not implemented, 12 combinations are available.

MMOD: Memory Mode Channel 0 (bit 1). When channel 0 is con-
figured for memory to/from memory transfers there is no

REQUEST

HANDSHAKE

signal to control the transfer timing. Instead, two auto-

matic transfer timing modes are selectable: burst (

MMOD = 1

) and

cycle steal (

MMOD = 0

). For burst memory to/from memory trans-

fers, the DMAC takes control of the bus continuously until the DMA
transfer completes (the byte count register is

). In

CYCLE STEAL

mode, the CPU is provided a cycle for each DMA byte transfer
cycle until the transfer is completed.

For channel 0 DMA with I/O source or destination, the selected

REQUEST HANDSHAKE

signal times the transfer and

MMOD

ignored.

MMOD

is cleared to

during

RESET

Table 17. Channel 0 Source

SM1

SM0

Memory I/O

Memory Increment/Decrement

Memory

fixed

I/O

fixed

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

DMA/WAIT Control Register (DCNTL)

DCNTL

controls the insertion of wait states into DMAC (and CPU)

accesses of memory or I/O. DCNTL also defines the Request sig-
nal for each channel as level or edge sense.

DCNTL

also sets the

DMA transfer mode for channel 1, which is limited to memory to/
from I/O transfers.

Figure 67. DMA/WAIT Control Register (DCNTL: I/O Address = 32h

MWI1, MWI0: Memory Wait Insertion (bits 7-6). Specifies the
number of wait states introduced into CPU or DMAC memory
access cycles.

MWI1

and

MWI0

are set to

during

RESET

. (See

Wait-State Generator for details.)

IWI1, IWI0: I/O Wait Insertion (bits 5-4). Specifies the number of
wait states introduced into CPU or DMAC I/O access cycles.

IWI1

and

IWI0

are set to

during

RESET

. See Wait-State Generator for

details.

DMS1, DMS0: DMA Request Sense (bits 3-2).

DMS1

and

DMS0

specify the DMA request sense for channel 0 and channel 1
respectively. When reset to

, the input is level sense. When set to

, the input is edge sense.

DMS1

and

DMS0

are cleared to

during

RESET

DMA/WAIT Control Register (DCNTL: I/O Address = 32h)

Bit

MWI1

IWI0

R/W

DMS1 DMS0

DIM1

R/W

MWI0

IWI1

DIM0

R/W

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

Typically, for an input/source device, the associated DMS bit
should be programmed as

for level sense because the device

undertakes a relatively long period to update its

REQUEST

signal

after the DMA channel reads data from it in the first of the two
machine cycles involved in transferring a byte.

An output/destination device takes much less time to update its

REQUEST

signal, after the DMA channel starts a

WRITE

operation

to it, as the second machine cycle of the two cycles involved in
transferring a byte. With zero-wait state I/O cycles, which apply
only to the ASCIs, it is impossible for a device to update its

REQUEST

signal in time, and edge sensing must be used.

With one-wait-state I/O cycles (the fastest possible except for the
ASCIs), it is unlikely that an output device is able to update its

REQUEST

in time, and edge sense is required for output to the

ESCC and bidirectional Centronics controller, and is recommended
for external output devices connected to

OUT

DREQ

With two or more wait states in I/O cycles, external output devices
on

OUT

DREQ

can use edge or level sense depending on their

characteristics; edge sense is still recommended for output on the
ESCC and bidirectional Centronics controller.

DIM1, DIM0: DMA Channel 1 I/O and Memory Mode (bits 1-0).
Specifies the source/destination and address modifier for channel
1 memory to/from I/O transfer modes.

DIM1

and

DIM0

are cleared

during

RESET

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

Interrupt Vector Low Register

Mnemonic: IL

Address 33

Bits

are used as bits

of the synthesized interrupt vec-

tor during interrupts for the

INT1

and

INT2

pins and for the DMAs,

ASCIs,

PRTs

, and

CSIO

. These three bits are cleared to

during

RESET

(Figure ).

Figure 68. Interrupt Vector Low Register (IL: I/O Address = 33h)

Table 18. Channel 1 Transfer Mode

DIM1 DMI0 Transfer Mode Address Increment/Decrement
0

Memory

®I/O

MAR1 +1, IAR1 fixed

Memory

®I/O

MAR11, IAR1 fixed

I/O

®Memory

IAR1 fixed, MAR1 + 1

I/O

®Memory

IAR1 fixed, MAR1 1

Interrupt Vector Low Register (IL: I/O Address = 33h)

Bit

IL 7

IL 6

Interrupt Source Dependent Code

IL 5

R/W

Programmable

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

Int/TRAP Control Register

Mnemonics ITC

Address 34

INT/TRAP Control Register (ITC, I/O Address 34h)

This register is used in handling

TRAP

interrupts and to enable or

disable Maskable Interrupt Level 0 and the

INT1

and

INT2

pins.

Figure 69. Int/TRAP Control Register

TRAP (bit 7). This bit is set to

when an undefined op code is

fetched.

TRAP

can be reset under program control by writing it with

, however, it cannot be written with

under program control.

TRAP

is reset to

during

RESET

UFO: Undefined Fetch Object (bit 6). When a

TRAP

interrupt

occurs, the contents of a

UFO

allow the starting address of the

undefined instruction to be determined. However, the

TRAP

may

occur on either the second or third byte of the op code. A

UFO

allows the stacked Program Counter (

) value to be correctly

adjusted. If

UFO = 0

, the first op code should be interpreted as the

stacked

PC-1

. If

UFO = 1

, the first op code address is stacked

PC-2

UFO

READ-ONLY

Bit

TRAP UFO

R/W

ITE2 ITE1 ITE0

R/W

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

ITE2, 1, 0: Interrupt Enable 2, 1, 0 (bits 2-0).

ITE2

and

ITE1

enable and disable the external interrupt inputs

INT2

and

INT1

respectively.

ITE0

enables and disables interrupts from the on-chip

ESCC, CTCs and bidirectional Centronics controller as well as the
external interrupt input

INT0

. A

in a bit enables the corresponding

interrupt level while a

disables it. A

RESET

clears

ITE0

and

clears

ITE1

and

ITE2

TRAP Interrupt

The Z80180 generates a nonmaskable (not affected by the state of

IEF1

)

TRAP

interrupt when an undefined op code fetch occurs. This

feature can be used to increase software reliability, implement an
extended instruction set, or both.

TRAP

may occur during op code

fetch cycles and also if an undefined op code is fetched during the
interrupt acknowledge cycle for

INT0

when Mode 0 is used.

When a

TRAP

interrupt occurs, the Z80180 operates as follows:

1. The

TRAP

bit in the Interrupt

TRAP

/Control (

ITC

) register is set

2. The current Program Counter (

) value, reflecting the location

of the undefined op code, is saved on the stack.

3. The Z80180 vectors to logical address

If logical address

0000h

is mapped to physical

address

00000h

, the vector is the same as for

RESET

. In this case, testing the

TRAP

bit in

ITC

reveals whether the restart at physical address

00000h

was caused by

RESET

TRAP

All

TRAP

interrupts occur after fetching an undefined second op

code byte following one of the prefix op codes

CBh

DDh

EDh

, or

FDh

, or after fetching an undefined third op code byte following one

of the double-prefix op codes

DDCBh

FDCBh

Note:

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

The state of the Undefined Fetch Object (

UFO

) bit in

ITC

allows

TRAP

software to correctly adjust the stacked

, depending on

whether the second or third byte of the op code generated the

TRAP

. If

UFO = 0

, the starting address of the invalid instruction is

equal to the stacked

PC-1

. If

UFO = 1

, the starting address of the

invalid instruction is equal to the stacked

PC-2

Figure 70. TRAP Timing--2

Op Code Undefined

)

0000h

SP-1

Undefined

MREQ

SP-2

Op Code

2nd Op Code

Fetch Cycle

PC Stacking

Op Code

Fetch Cycle

Restart

from 0000h

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

Figure 71. TRAP Timing--3

Op Code Undefined

TRAP Timing--2

Op Code Undefined

TRAP Timing--3

Op Code Undefined

)

0000h

SP-1

Undefined

MREQ

SP-2

Op Code

PC-1

3nd Op Code

Fetch Cycle

PC Stacking

Op Code

Fetch Cycle

Restart

Memory

IX + d, IY + d

READ Cycle

from 0000h

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

Refresh Control Register

Mnemonic RCR

Address 36

Figure 72. Refresh Control Register (RCA: I/O Address = 36h)

The RCR specifies the interval and length of refresh cycles, while
enabling or disabling the refresh function.

REFE: Refresh Enable (bit 7).

REFE = 0

disables the refresh con-

troller, while

REFE = 1

enables refresh cycle insertion.

REFE

is set

during

RESET

REFW: Refresh Wait (bit 6).

REFW = 0

causes the refresh cycle to

be two clocks in duration.

REFW = 1

causes the refresh cycle to be

three clocks in duration by adding a refresh wait cycle (

TRW

REFW

is set to

during

RESET

CYC1, 0: Cycle Interval (bit 1,0).

CYC1

and

CYC0

specify the

interval (in clock cycles) between refresh cycles. In the case of
dynamic RAMs requiring 128 refresh cycles every 2 ms (or 256
cycles in every 4 ms), the required refresh interval is less than or

Refresh Control Register (RCA: I/O Address = 36h)

Reserved

Cyc1

Cyc0

REFW

REFE

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

100

equal to 15.625 µs. The underlined values indicate the best refresh
interval depending on CPU clock frequency.

CYC0

and

CYC1

are

cleared to

during

RESET

(see DRAM Refresh Intervals).

Refresh Control and RESET

After

RESET

, based on the initialized value of

RCR

, refresh cycles

occur with an interval of 10 clock cycles and be 3 clock cycles in
duration.

Dynamic RAM Refresh Operation

REFRESH CYCLE

insertion is stopped when the CPU is in the

following states:

a. During

RESET

b. When the bus is released in response to

BUSREQ

c. During

SLEEP

mode

d. During

WAIT

states

2. Refresh cycles are suppressed when the bus is released in

response to

BUSREQ

. However, the refresh timer continues to

Table 19. DRAM Refresh Intervals

Insertion Interval

Time Interval

CYC1 CYC0

Ø: 10 MHz 8 MHz

6 MHz

4 MHz

2.5 MHz

10 states

(1.0 µs)*

(1.25 µs)* 1.66 µs 2.5 µs

4.0 µs

20 states

(2.0 µs)*

(2.5 µs)*

3.3 µs

5.0 µs

8.0 µs

40 states

(4.0 µs)*

(5.0 µs)*

6.6 µs

10.0 µs 16.0 µs

80 states

(8.0 µs)*

(10.0 µs)* 13.3 µs 20.0 µs 32.0 µs

OTE

: *Calculated interval.

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

101

operate. The time at which the first refresh cycle occurs after
the Z80180 reacquires the bus depends on the refresh timer,
and possesses no timing relationship with the bus exchange.

3. Refresh cycles are suppressed during

SLEEP

mode. If a

refresh cycle is requested during

SLEEP

mode, the refresh

cycle request is internally latched (until replaced with the next
refresh request). The latched refresh cycle is inserted at the
end of the first machine cycle after

SLEEP

mode is exited. After

this initial cycle, the time at which the next refresh cycle occurs
depends on the refresh time and carries no relationship with
the exit from

SLEEP

mode.

4. The refresh address is incremented by one for each successful

refresh cycle, not for each refresh. Independent of the number
of missed refresh requests, each refresh bus cycle uses a
refresh address incremented by one from that of the previous
refresh bus cycles.

MMU Common Base Register

Mnemonic CBR

Address 38

MMU Common Base Register (CBR). CBR

specifies the base

address (on 4-KB boundaries) used to generate a 20-bit physical
address for Common Area 1 accesses. All bits of

CBR

are reset to

during

RESET

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

102

Figure 73. MMU Bank Base Register (BBR: I/O Address = 39h)

MMU Bank Base Register (BBR)

Mnemonic BBR

Address 39

BBR

specifies the base address (on 4-KB boundaries) used to gen-

erate a 19-bit physical address for Bank Area accesses. All bits of

BBR

are reset to

during

RESET

Figure 74. MMU Bank Base Register (BBR: I/O Address = 39h)

MMU Bank Base Register (BBR: I/O Address = 39h)

Bit

CB7

CB6

R/W

CB5

CB4

CB2

CB1

CB0

R/W

CB3

R/W

Bit

BB7

BB6

R/W

BB5

BB4

BB2

BB1

BB0

R/W

BB3

R/W

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

103

MMU Common/Bank Area Register (CBAR)

Mnemonic CBAR

Address 3A

CBAR

specifies boundaries within the Z80180 64-KB logical

address space for up to three areas: Common Area, Bank Area
and Common Area 1.

Figure 75. MMU Common/Bank Area Register (CBAR: I/O Address =

3 AH

CA3CA0:CA (bits 7-4).

specifies the start (Low) address (on

4-KB boundaries) for the Common Area 1, and also determines the
most recent address of the Bank Area. All bits of CA are set to

during

RESET

BABA0 (bits 3-0).

specifies the start (Low) address (on 4-KB

boundaries) for the Bank Area, and also determines the most
recent address of the Common Area 0. All bits of

are set to

during

RESET

MMU Common/Bank Area Register (CBAR: I/O Address = 3 AH

Bit

CA3

CA2

R/W

CA1

CA0

BA2

BA1

BA0

R/W

BA3

R/W

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

104

Operation Mode Control Register

Mnemonic OMCR

Address 3E

The Z80180 is descended from two different ancestor processors,
ZiLOG's original Z80 and the Hitachi 64180. The Operating Mode
Control Register (OMCR) can be programmed to select between
certain differences between the Z80 and the 64180.

Figure 76. Operating Control Register(OMCR: I/O Address = 3Eh

M1E (M1 Enable). This bit controls the

output and is set to a

during reset.

When

M1E = 1

, the

output is asserted Low during the op code

fetch cycle, the

INT0

acknowledge cycle, and the first machine

cycle of the

NMI

acknowledge.

On the Z80180, this choice makes the processor fetch a

RETI

instruction one time only, and when fetching a

RETI

from zero-wait-

Operating Control Register(OMCR: I/O Address = 3Eh)

Reserved

D6 D5 --

IOC (R/W)

M1TE (W)

M1E (R/W)

-- -- -- --

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

105

state memory, uses three clock machine cycles which are not fully
Z80-timing compatible, but are compatible with the on-chip CTCs.

When

MIE = 0

, the processor does not drive

Low during instruc-

tion fetch cycles. After fetching a

RETI

instruction one time only

with normal timing, the processor refetches the instruction using
fully Z80-compatible cycles that include driving

Low. As a result,

some external Z80 peripherals may require properly decoded

RETI

instruction.

Figure 77. RETI Instruction Sequence with MIE=0

RET

I Instruction Sequence with MIE=0

)

PC+1

EDh

4Dh

EDh

4Dh

MREQ

Z80180

Microprocessor Unit

PS014003-0603

Functional Description

106

I/O Control Register (ICR)

ICR

allows relocating of the internal I/O addresses.

ICR

also con-

trols enabling/disabling of the

IOSTOP

mode (Figure ).

Figure 78. I/O Control Register (ICR: I/O Address = 3Fh)

IOA7, 6: I/O Address Relocation (bits 7,6)

IOA7

and

IOA6

relocate internal I/O as illustrated in Figure 74.

The high-order 8 bits of 16-bit internal I/O
address are always 0.

IOA7

and

IOA6

are cleared

during

RESET

I/O Control Register (ICR: I/O Address = 3Fh)

IOA7

IOA6

IOSTP

Bit

R/W

Note:

Z80180

Microprocessor Unit

Functional Description

PS014002-0403

111

Ordering Information

For fast results, contact your local ZiLOG sales office for assis-
tance in ordering the part required.

Codes

Example:

The Z80180 is a 10-MHz DIP, 0ºC to 70ºC, with Plastic Standard
Flow.

Table 20. Ordering Information

Z80180
6, 8, 10, 20, 33 MHz
Z8018010FSC
Z8018010PSC
Z8018010VSC

Package

F = Plastic Quad Flatpack
P = Plastic Dual In Line
V = Plastic Leaded Chip Carrier

Temperature

S = 0°C to +70°C

Speed

6 = 6 MHz
8 = 8 MHz
10 = 10 MHz

Environmental

C = Plastic Standard

Document Outline

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Document Outline

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