1
GENERAL DESCRIPTION
DC-4021-05
(7-07-92)
The Zilog Enhanced Serial Communications Controller,
Z80230 ESCC, is a pin and software compatible CMOS
member of the SCC family introduced by Zilog in 1981. The
ESCC is a dual-channel, full-duplex data communications
controller capable of supporting a wide range of popular
protocols. The ESCC is built from Zilog's industry standard
SCC core and is compatible with designs using Zilog's
SCC to receive and transmit data. It has many improve-
ments that significantly reduce CPU overhead. The addi-
tion of a 4-byte transmit FIFO and an 8-byte receive FIFO
significantly reduces the overhead required to provide
data to, and get data from, the transmitters and receivers.
The ESCC also has many features that improve packet
handling in SDLC mode. The ESCC will automatically:
transmit a flag before the data, reset the Tx Underrun/EOM
latch, force the TxD pin high at the appropriate time when
using NRZI encoding, deassert the /RTS pin after the
closing flag, and better handle ABORTed frames when
using the 10x19 status FIFO. The combination of these
features along with the deeper data FIFOs significantly
simplifies SDLC driver software.
C
USTOMER
P
ROCUREMENT
S
PECIFICATION
The CPU hardware interface has been simplified by reliev-
ing the databus setup time requirement and supporting
the software generation of the interrupt acknowledge sig-
nal (INTACK). These changes allow an interface with less
external logic to many microprocessor families while main-
taining compatibility with existing designs. I/O handling of
the ESCC is improved over the SCC with faster response
of the /INT and /DTR//REQ pins.
The many enhancements added to the ESCC permits a
system design that increases overall system performance
with better data handling and less interface logic.
Notes:
All Signals with a preceding front slash, "/", are active Low, e.g.:
B//W (WORD is active Low); /B/W (BYTE is active Low, only).
Power connections follow conventional descriptions below:
Connection
Circuit
Device
Power
V
CC
V
DD
Ground
GND
V
SS
Z80230
ESCC
TM
E
NHANCED
S
ERIAL
C
OMMUNICATION
C
ONTROLLER
2
GENERAL DESCRIPTION
(Continued)
1
2
9
3
4
5
6
7
8
40
39
38
37
36
35
34
33
32
AD0
AD2
CS1
AD4
AD6
/DS
/AS
R//W
/CS0
AD1
31
30
29
28
27
14
10
11
12
13
GND
/W//REQB
/SYNCB
/RTxCB
RxDB
AD3
AD5
AD7
/INT
IEO
IEI
/INTACK
VCC
/W//REQA
/SYNCA
/RTxCA
RxDA
/TRxCA
TxDA
/DTR//REQA
/RTSA
/CTSA
/DCDA
PCLK
15
16
17
18
19
20
/TRxCB
TxDB
/DTR//REQB
RTSB
/CTSB
/DCDB
26
25
24
23
22
21
Z80230
Z80230 DIP Pin Assignments
NC
/DTR//REQA
/RTSA
/CTSA
/DCDA
PCLK
/DCDB
/CTSB
/RTSB
/DTR//REQB
NC
/INT
AD7
AD5
AD3
AD0
AD2
AD4
AD6
/DS
/AS
AD1
6
Z80230
IEO
IEI
/INTACK
VCC
/W//REQA
/SYNCA
/RTxCA
RxDA
/TRxCA
TxDA
NC
R//W
/CS0
/CS1
NC
GND
/W//REQB
/SYNCB
/RTxCB
RxDB
/TRxCB
TxDB
5
4
3
2
1 44 43 42 41 40
18 19 20 21 22 23 24 25 26 27 28
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
Z80230 PLCC Pin Assignments
3
+5V
From Output
Under Test
100 pf
250
A
2.1 K
ABSOLUTE MAXIMUM RATINGS
V
CC
Supply Voltage range ......................... -0.3V to +7.0V
Voltages on all pins
with respect to GND ........................ -0.3V to V
CC
+0.3V
Operating Ambient
Temperature......................... See Ordering Information
Storage Temperature ............................ -65
C to +150
C
Stresses greater than those listed under Absolute Maxi-
mum Ratings may cause permanent damage to the de-
vice. This is a stress rating only; operation of the device at
any condition above those indicated in the operational
sections of these specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods
may affect device reliability.
STANDARD TEST CONDITIONS
The DC Characteristics and capacitance sections below
apply for the following standard test conditions, unless
otherwise noted. All voltages are referenced to GND.
Positive current flows into the referenced pin.
Standard conditions are as follows:
s
+4.50 V
V
CC
+ 5.50 V
s
GND = 0 V
s
T
A
as specified in Ordering Information
Standard Test Load
+5V
From Output
50 pf
2.2 K
Open-Drain Test Load
CAPACITANCE
Symbol
Parameter
Min
Max
Unit
Test Condition
C
IN
Input Capacitance
10
pF
Unmeasured pins
C
OUT
Output Capacitance
15
pF
returned to ground.
C
I/O
Bidirectional Capacitance
20
pF
Note:
f = 1 MHz, over specified temperature range.
MISCELLANEOUS
Gate Count - 11,000
4
DC CHARACTERISTICS
Z80230
Symbol
Parameter
Min
Typ
Max
Unit
Condition
V
IH
Input High Voltage
2.2
V
CC
+0.3
V
V
IL
Input Low Voltage
-0.3
0.8
V
V
OH1
Output High Voltage
2.4
V
I
OH
= -1.6mA
V
OH2
Output High Voltage
V
CC
-0.8
V
I
OH
= -250
A
V
OL
Output Low Voltage
0.4
V
I
OL
= +2.0mA
I
IL
Input Leakage
10.0
A
0.4 <V
IN
<+2.4V
I
OL
Output Leakage
10.0
A
0.4 <V
OUT
<+2.4V
I
CC1
V
CC
Supply Current
4
10 (8.5 MHz)
mA
5
12 (10 MHz)
mA
V
CC
=5V V
IH
=4.8 V
IL
=0.2V
7
15 (16 MHz)
mA
Crystal Oscillators off
9
20 (20 MHz)
mA
I
CC(OSC)
Crystal OSC Current
6
mA
Current for each osc.
in addition to I
CC1
Notes:
[1] V
CC
= 5V
10% unless otherwise specified, over specified temperature range.
[2] Typical I
CC
was measured with oscillator off.
[3] No I
CC
(osc) max is specified due to dependency on the external circuit.
5
AC CHARACTERISTICS
Z80230 Read and Write Timing Diagrams
Z80230 Read/Write Timing Diagram
1
3
4
5
7
6
2
8
9
11
12
13
14
10
10
15
16
17
15
16
19
21
22
24
25
26
27
28
40
41
42
43
44
/AS
/CS0
CS1
/INTACK
R//W
Read
R//W
Write
/DS
AD7-AD0
Write
AD7-AD0
Read
/W//REQ
Wait
/W//REQ
Request
/DTR//REQ
Request
/INT
PCLK
18
20
23
6
/AS
/INTACK
/DS
AD7-AD0
IEI
IEO
/INT
7
8
30
29
19
31
32
33
36
35
34
20
22
Active
Valid
Z80230 Interrupt Acknowledge Timing Diagram
/AS
/DS
38
37
35
Z80230 Reset Timing Diagram
7
AC CHARACTERISTICS
Z80230 Read/Write Timing Table
10 MHz
16 MHz
No
Symbol
Parameter
Min
Max
Min
Max
Notes*
1
TwAS
/AS Low Width
30
20
2
TdDS(AS)
/DS Rise to /AS Fall Delay
10
10
[1]
3
TsCSO(AS)
/CS0 to /AS Rise Setup Time
0
0
[1]
4
ThCSO(AS)
/CS0 to /AS Rise Hold Time
20
15
[1]
5
TsCS1(DS)
CS1 to /DS Fall Setup Time
50
35
[1]
6
ThCS1(DS)
CS1 to /DS Rise Hold Time
20
10
[1]
7
TslA(AS)
/INTACK to /AS Rise Setup Time
10
10
8
ThlA(AS)
/INTACK to /AS Rise Hold Time
125
100
9
TsRWR(DS)
R//W (Read) to /DS Fall Setup Time
50
30
10
ThRW(DS)
R//W to /DS Rise Hold Time
0
0
11
TsRWW(DS)
R//W (Write) to /DS Fall Setup Time
0
0
12
TdAS(DS)
/AS Rise to /DS Fall Delay
20
15
13
TwDSl
/DS Low Width
125
80
14
TrC
Valid Access Recovery Time
4TcPc
4TcPc
[2]
15
TsA(AS)
Address to /AS Rise Setup Time
10
10
[1]
16
ThA(AS)
Address to /AS Rise Hold Time
20
10
[1]
17
TsDW(DS)
Write Data to /DS Fall Setup Time
10
10
18
ThDW(DS)
Write Data to /DS Rise Hold Time
0
0
19
TdDS(DA)
/DS Fall to Data Active Delay
0
0
20
TdDSr(DR)
/DS Rise to Read Data Not Valid Delay
0
0
21
TdDSf(DR)
/DS Fall to Read Data Valid Delay
120
70
22
TdAS(DR)
/AS Rise to Read Data Valid Delay
190
110
23
TdDS(DRz)
/DS Rise to Read Data Float Delay
35
20
[3]
24
TdA(DR)
Address Required Valid to Read Data Valid Delay
210
100
25
TdDS(W)
/DS Fall to Wait Valid Delay
160
60
[4]
26
TdDSf(REQ)
/DS Fall to /W//REQ Not Valid Delay
160
60
27
TdDSr(REQ)
/DS Fall to /DTR//REQ Not Valid Delay
4TcPc
4TcPc
28
TdAS(INT)
/AS Rise to /INT Valid Delay
500
175
[4]
29
TdAS(DSA)
/AS Rise to /DS Fall (Acknowledge) Delay
225
50
[5]
30
TwDSA
/DS (Acknowledge) Low Width
125
75
31
TdDSA(DR)
/DS Fall (Acknowledge) to Read Data Valid Delay
70
32
TslEl(DSA)
IEI to /DS Fall (Acknowledge) Setup Time
80
50
33
ThlEl(DSA)
IEI to /DS Rise (Acknowledge) Hold Time
0
0
34
TdlEl(IEO)
IEI to IEO Delay
90
45
35
TdAS(IEO)
/AS Rise to IEO Delay
175
80
[6]
36
TdDSA(INT)
/DS Fall (Acknowledge) to /INT Inactive Delay
450
200
[4]
37
TdDS(ASQ)
/DS Rise to /AS Fall Delay for No Reset
15
10
38
TdASQ(DS)
/AS Rise to /DS Fall Delay for No Reset
15
10
39
TwRES
/AS and /DS Coincident Low for Reset
100
75
[7]
40
TwPCl
PCLK Low Width
40
100
26
1000
8
AC CHARACTERISTICS
Z80230 Read/Write Timing Table (Continued)
10 MHz
16 MHz
No
Symbol
Parameter
Min
Max
Min
Max
Notes*
41
TwPCh
PCLK High Width
40
1000
26
1000
42
TcPC
PCLK Cycle Time
100
2000
61
2000
43
TrPC
PCLK Rise Time
10
5
44
TfPC
PCLK Fall Time
10
5
Notes:
[1] Parameter does not apply to Interrupt Acknowledge transactions.
[2] Parameter applies only between transactions involving the SCC.
[3] Float delay is defined as the time required for a
0.5V change in the output with a maximum DC load and a minimum AC load.
[4] Open-drain output, measured with open-drain test load.
[5] Parameter is system dependent. For any Z-SCC in the daisy chain. TdAS(DSA) must be greater than the sum of TdAS(IEO) for the highest priority
device in the daisy chain. TslEl(DSA) for the Z-SCC, and TdlElf(IEO) for each device separating them in the daisy chain.
[6] Parameter applies only to a Z-SCC pulling INT Low at the beginning of the Interrupt Acknowledge transaction.
[7] Internal circuitry allows for the reset provided by the Z8 to be recognized as a reset by the Z-SCC. All timing references assume 2.0V for a logic
"1" and 0.8V for a logic "0".
* Units in nanoseconds (ns).
9
AC CHARACTERISTICS
Z80230 General Timing Diagram
1
2
3
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
22
PCLK
/W//REQ
Request
/W//REQ
Wait
/CTS//TRxC,
RTxC
Receive
RxD
/SYNC
External
TxD
/CTS//TRxC
Output
/RTxC
/CTS//TRxC
/CTS//TRxC,
/DCD
/SYNC
Input
21
/CTS//TRxC,
RTxC
Transmit
4
Z80230 General Timing Diagram
10
AC CHARACTERISTICS
Z80230 General Timing Table
10 MHz
16 MHz
No
Symbol
Parameter
Min
Max
Min
Max
Notes*
1
TdPC(REQ)
/PCLK Low to W/REQ Valid
200
110
2
TsPC(W)
/PCLK Low to Wait Inactive
300
180
3
TsRXC(PC)
/RxC High to /PCLK High Setup Time
NA
NA
[1,4]
4
TsRXD(RXCr)
RxD to /RxC High Setup Time
0
0
[1]
5
ThRXD(RxCr)
RxD to /RxC High Hold Time
125
60
[1]
6
TsRXD(RXCf)
RxD to /RxC Low Setup Time
0
0
[1,5]
7
ThRXD(RXCf)
RxD to /RxC Low Hold Time
125
60
[1,5]
8
TsSY(RXC)
SYNC to /RxC High Setup Time
-150
-100
[1]
9
ThSY(RXC)
SYNC to /RxC High Hold Time
5TcPc
5TcPc
[1]
10
TsTXC(PC)
/TxC Low to /PCLK High Setup Time
NA
NA
[2,4]
11
TdTXCf(TXD)
/TxC Low to TxD Delay
150
85
[2]
12
TdTxCr(TXD)
/TxC High to TxD Delay
150
85
[2,5]
13
TdTXD(TRX)
TxD to TRxC Delay
140
80
14
TwRTXh
RTxC High Width
120
80
[6]
15
TwRTXl
TRxC Low Width
120
80
[6]
16a
TcRTX
RTxC Cycle Time
400
244
[6,7]
16b
TxRX(DPLL)
DPLL Cycle Time Min
50
31
[7,8]
17
TcRTXX
Crystal Osc. Period
100
1000
100
1000
[3]
18
TwTRXh
TRxC High Width
120
80
[6]
19
TwTRXl
TRxC Low Width
120
80
[6]
20
TcTRX
TRxC Cycle Time
400
244
[6,7]
21
TwEXT
DCD or CTS Pulse Width
120
70
22
TwSY
SYNC Pulse Width
120
70
Notes:
[1] RxC is /RTxC or /TRxC, whichever is supplying the receive clock.
[2] TxC is /TRxC or /RTxC, whichever is supplying the transmit clock.
[3] Both /RTxC and /SYNC have 30 pf capacitors to ground connected to them.
[4] Synchronization of RxC to PCLK is eliminated in divide by four operation.
[5] Parameter applies only to FM encoding/decoding.
[6] Parameter applies only for transmitter and receiver; DPLL and baud rate generator timing requirements are identical to case PCLK requirements.
[7] The maximum receive or transmit data rate is 1/4 PCLK.
[8] Applies to DPLL clock source only. Maximum data rate of 1/4 PCLK still applies. DPLL clock should have a 50% duty cycle.
* Units in nanoseconds (ns).
11
AC CHARACTERISTICS
Z80230 System Timing Diagram
Z80230 System Timing Diagram
1
2
3
4
5
9
10
8
7
6
/RTxC, /TRxC
Receive
/W//REQ
Request
/W//REQ
Wait
/SYNC
Output
/INT
/TRxC, /RTxC
Transmit
/W//REQ
Request
/W//REQ
Wait
/DTR//REQ
Request
/INT
/CTS, /DCD
/SYNC
Input
/INT
12
AC CHARACTERISTICS
Z80230 System Timing Table
10 MHz
16 MHz
No
Symbol
Parameter
Min
Max
Min
Max
Notes*
1
TdRXC(REQ)
/RxC High to W/REQ Valid
13
17
13
17
[2]
2
TdRXC(W)
/RxC High to Wait Inactive
13
19
13
19
[1,2]
3
TdRdXC(SY)
/RxC High to SYNC Valid
4
7
4
7
[2]
4b
TdRXC(INT), Z80230
/RxC High to INT Valid
13
17
13
17
[1,2]
2
3
+2
+3
[4]
5
TdTXC(REQ)
/TxC Low to W/REQ Valid
11
14
11
14
[3]
6
TdTXC(W)
/TxC Low to Wait Inactive
8
14
8
14
[1,3]
7
TdTXC(DRQ)
/Txc Low to DTR/REQ Valid
9
12
9
12
[3]
8b
TdTXC(INT), Z80230
/TxC Low to /INT Valid
7
9
7
9
[1,3]
+2
+3
+2
+3
[4]
9
TdSY(INT)
SYNC to INT Valid
2
6
2
6
[1]
+2
+3
+2
+3
[4]
10b
TdEXT(INT), Z80230
2
3
3
8
[1,4]
Notes:
* Units equal to TcPc.
[1] Open drain-output, measured with open-drain test load.
[2] /RxC is /RTxC or /TRxC, whichever is supplying the receive clock.
[3] /TxC is /TRxC or /RTxC, whichever is supplying the transmit clock.
[4] Units equal to /AS.
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