PRS000502-1005

P R E L I M I N A R Y

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PRS000502-1005

P R E L I M I N A R Y

Flash Memory Programming Overview

Z8FMC16 MCU

Programming Specification

Flash Memory Programming Overview

The Z8 Encore!

Z8FMC16 Motor Control features a Flash program memory selections

of 8KB or 16KB. By using Flash memory, you have the ability to easily update the code.
The Z8 Encore!

features an on-chip Flash controller that typically manages the timing of

Flash control signals for programming, page erase, and mass erase operations. The Flash
controller can also be bypassed to allow direct control of Flash signals via the general
purpose input/output (GPIO) pins. Flash memory can be programmed faster by controlling
the Flash memory signals directly. Bypassing the Flash controller is beneficial when
programming a large number of devices, and is most likely to be used by third party
vendors who are developing the multi-site gang programmers.

Bypassing the Flash Controller

Flash controller bypass mode is enabled by writing the following three bytes of instruction
to the on-chip debugger (OCD) via the DBG interface:

1. 80H - This instruction initiates auto-baud calculation of the DBG interface data and

clock rate.

2. F0H - OCD writes testmode register command.

3. 04H - Data to be written to the testmode register. This data enables the Flash

controller bypass mode.

Flash Memory Control Signals

Depending on the size (number of bytes) available in the Flash memory, the Flash memory
uses fourty two signals for its direct interfacing.

16 signals for the address lines.

8 signals for data input.

8 signals for data output.

10 signals for control operations.

The Flash memory control signals are listed and described in

Table 1

PRS000502-1005

P R E L I M I N A R Y

Flash Memory Programming Overview

Z8FMC16 MCU

Programming Specification

Flash Memory Operations

When bypassing the Flash controller, all Flash memory operations (read, program, page
erase, and mass erase) are available. The mode of operation is set by the Flash memory
control signals as described in

Table 2

The selection of the Flash main memory or the Flash information area depends on the
IFREN signal as described in

Table 3

Table 1. Flash Memory Control Signals

Signal

Direction

Description

XADDR[9:0]

X address input selects a row. XADDR[9:0] corresponds to the upper
10 bits of the program memory address space (PROGMEM[15:6]).
For Z8 Encore!

devices with less than 64KB of program memory, the

unused upper address bits must be set to 0.

YADDR[5:0]

Y address input selects one byte within a row. YADDR[5:0]
corresponds to the lower 6 bits of the program memory address space
(PROGMEM[5:0]).

DIN[7:0]

Data input.

DOUT[7:0]

Data output.

X address enable.

Y address enable.

Sense amplifier enable.

Output enable.

ERASE

Erase enable. This signal is used to select erase operations.

MAS1

Mass erase select. This signal is used to distinguish between page
erase and mass erase operations.

PROG

Program enable. This signal is used to select a program operation.

NVSTR

Non-volatile store enable. This signal is used during page erase, mass
erase, and programming operations.

TMR

This signal should be set to 1 during all operations.

IFREN

Information area select.

PRS000502-1005

P R E L I M I N A R Y

Flash Memory Programming Overview

Z8FMC16 MCU

Programming Specification

Flash Bypass Mode Register Structure

For using Flash controller bypass mode for all package sizes, the signals must be
registered internally. This allows all data access to occur through pin PWM2L and Port A
[6:0]. Three other pins (PWM2H, PWM1L, and PWM1H), selects one of the input data
registers or the data output register as shown in

Table 4

Table 2. Flash Mode Truth Table

Mode

PROG ERASE MAS1

NVSTR TMR

IFREN

Read

L/H

Program

L/H

Page Erase

L/H

Mass Erase

L/H

See

Table 3

for IFREN signal operation information.

Table 3. IFREN Signal Truth Table

Mode

IFREN = 1

IFREN = 0

Read

Read Information Area

Read Main Memory

Program

Program Information Area Program Main Memory

Page Erase

Page Erase Information
Area

Page Erase Main Memory

Mass Erase

Mass Erase Information
Area

Mass Erase Main Memory

PRS000502-1005

P R E L I M I N A R Y

Flash Memory Programming Overview

Z8FMC16 MCU

Programming Specification

Table 4. Control Registers in Flash Bypass Mode

Input/Output

Register Select [PWM2H, PWM1L, PWM1H]

000

001

010

011

100

101

110-111

Input

Output

Input

PWM2L

XADDR[9] XADDR[1] DIN[7]

TMR

DOUT[7]

NOP

Port A6

XADDR[8] XADDR[0] DIN[6]

IFREN

DOUT[6]

NOP

Port A5

XADDR[7] YADDR[5] DIN[5]

NOP

DOUT[5]

NOP

Port A4

XADDR[6] YADDR[4] DIN[4]

NOP

DOUT[4]

NOP

Port A3

XADDR[5] YADDR[3] DIN[3]

ERASE

NOP

DOUT[3]

NOP

Port A2

XADDR[4] YADDR[2] DIN[2]

PROG

NOP

DOUT[2]

NOP

Port A1

XADDR[3] YADDR[1] DIN[1]

MAS1

NOP

DOUT[1]

NOP

Port A0

XADDR[2] YADDR[0] DIN[0]

NVSTR

NOP

DOUT[0]

NOP

PRS000502-1005

P R E L I M I N A R Y

Flash Memory Programming Overview

Z8FMC16 MCU

Programming Specification

Flash Bypass Mode Register Structure

Figure 1

illustrates the multiplexed register structure that allows access to all Flash

memory signals through GPIO ports.

Bypass Mode Register Read Timing

Figure 2

illustrates the timing of a read operation using the Flash controller bypass mode

registers. While reading data, output data is latched into the output register on the first

Figure 1. Flash Bypass Mode Register Structure

PortA0

PortA1

PortA2

PortA3

PortA4

PortA5

PortA6

PWM2L

PWM2H

PWM1L

PWM1H

Data

Input/Output

Select

XADDR[9:0]

YADDR[5:0]

DIN[7:0]

DOUT[7:0]

Flash

Registers

XE
YE
OE
SE
ERASE
PROG
MAS1
NVSTR

TMR
IFREN

PRS000502-1005

P R E L I M I N A R Y

Flash Memory Programming Overview

Z8FMC16 MCU

Programming Specification

clock edge. The data is read during the next clock period. Mode selector comprises of the
following pins: PWM2H, PWM1L, and PWM1H.

Bypass Mode Register Write Timing

Figure 3

illustrates the timing of a write operation using the Flash controller bypass mode

registers. When writing data into the registers, the data is latched on the rising edge of
XIN.

Flash Row Programming

The Flash memory can be programmed either as a single byte at a time or as a row of bytes
at a time. Multi-byte row programming allows programming of a full row of Flash
memory without incurring all of the programming setup and recovery time for each byte.
During row programming, the Flash memorys PROG and NVSTR signals are

Figure 2. Bypass Mode Register Read Timing

Figure 3. Bypass Mode Register Write Timing

101

XIN

Selector

Port driven

by Chip

Data Latched in

Output Register

Data

Mode

XIN

Mode

Selector

Port driven

externally

Data latched in selected
register on rising edge of Xin

PRS000502-1005

P R E L I M I N A R Y

Flash Memory Programming Overview

Z8FMC16 MCU

Programming Specification

continuously asserted until all bytes in a row are programmed. This allows the row to be
programmed faster than if these signals are deasserted after programming each byte.

During row programming, you must ensure that the cumulative programming high voltage
period does not exceed the specification limits for a row.

Flash Memory Timing

Table 5

and

Figures 4

through

Figure 7

provides the detailed timing information on

accessing the Flash memory in Flash controller bypass mode.

The same address (byte) cannot be programmed more than twice before
the next erase.

Table 5. Flash Memory Timing Parameters

Parameter

Symbol

Min.

Max.

Unit

X address access time

Txa

Y address access time

Tya

OE access time

Toa

PROG/ERASE to NVSTR setup time

Tnvs

NVSTR hold time

Tnvh

NVSTR hold time (Mass Erase)

Tnvh1

100

NVSTR to program setup time

Tpgs

Program hold time

Tpgh

Byte program time

Tprog

Address / Data setup time

Tads

Address / Data hold time

Tadh

Recovery time

Trcv

Cumulative program high voltage period

Thv

Erase time

Terase

Mass Erase time

Tme

200

Thv is the cumulative high voltage programming time for a single row before the next erase.

Caution:

PRS000502-1005

P R E L I M I N A R Y

Flash Memory Programming Overview

Z8FMC16 MCU

Programming Specification

Flash Program Timing

Figure 5

illustrates the Flash programming operation for three bytes on a single row. The

XADDR is unchanged while PROG and NVSTR are high, but the YADDR changes three
times to identify three different bytes in a single row.

Figure 5. Flash Byte Program Timing

XADDR

YADDR

DIN

PROG

NVSTR

SE = 0, OE = 0, ERASE = 0, MAS1 = 0, TMR = 1

Tnvs

Tpgs

Tprog

Tads

Tadh

Tpgh

Tnvh

Trcv

Thv

IFREN

PRS000502-1005

P R E L I M I N A R Y

Flash Memory Programming Overview

Z8FMC16 MCU

Programming Specification

Flash Mass Erase Timing

Figure 7

illustrates the timing of a Flash mass erase operation.With IFREN driven high

(1), the mass erase operation will erase both the main memory and the information area.
With IFREN driven low (0), the mass erase operation will erase only the main memory.

Figure 7. Flash Mass Erase Timing

XADDR

ERASE

NVSTR

YE = 0, SE = 0, OE = 0, PROG = 0, TMR = 1

Tnvs

Tme

Tnvh1

Trcv

MAS1

IFREN

PRS000502-1005

P R E L I M I N A R Y

Flash Memory Programming Overview

Z8FMC16 MCU

Programming Specification

Z8FMC16100 Flash Programming Flowchart

Figure 8 illustrates an example flowchart for read and write operations.

Figure 8. Z8FMC16100 Flash Gang Programming Flow

Z8FMC16100 Flash Programming Flowchart

* The Values f or FFREQH and FFREQL are based
on a 20MHz clock source. This v alue is set by the
f ollowing equation

{FFREQH[7:0], FFREQL[7:0]} =(Clock Frequency )/
1000

0x4e20= (20 MHz)/1000

Do not use less then a 32kHz clock source.

START

RESET&

DBG Low

Release

DBG

XIN is

Sy sClk

Wait f or

break

Release

RESET

Write OCD

0x80

Mass
Erase

Flash?

Write OCD

0x80

Write OCD

0xF0

Write OCD

0x04

Autobaud

250 ms

N
o

Val ue for Wr

Tes tmode

Flash

Controller

By passed

Autobaud

5 ms

SEL = 0x04

DIN = 0x80

Set

TMR

TEST

Wr/Rd

Memory ?

SEL = 0x00

DIN = addr[15:8]

SEL = 0x03

DIN = 0x84

5 us

SEL=0x03

DIN = 0x85

10 us

SEL= 0x03
DIN=0xF0

30 us

Wr Done

Write OCD

0x08,
0x0F,
0x86,
0x01,

0xE2

OSCCT L E2

Write OCD

0x08,
0x0F,
0x86,
0x01,

0x18

OSCCT L 18

Write OCD

0x08,
0x0F,
0x86,
0x01,

0xE7

OSCCT L E7

Write OCD

0x08,
0x0F,

0xFA,

0x01,

0x4E

FFREQH

Write OCD

0x08,
0x0F,
0xFB,
0x01,

0x20

FFREQL

Write OCD

0x08,
0x0F,
0xF8,
0x01,

0x73

FCTL 73

Unlock step 1

Write OCD

0x08,
0x0F,
0xF8,
0x01,

0x8C

FCTL 8C

Unlock step 2

Write OCD

0x08,
0x0F,
0xF8,
0x01,

0x63

FCTL 63

Iss ues Mass erase

Write OCD

0x80

Autobaud

Wr Testmode

5 us

1 us

20ns

STOP

45 ns

SEL = 0x05

DOUT = data[7:0]

Rd Loop

Done

SEL = 0x01

DIN=addr[7:0]

SEL = 0x01

DIN=addr[7:0]

SEL = 0x02

DIN=data[7:0]

SEL = 0x03

DIN=0xC5

SEL=0x03

DIN = 0x85

SEL=0x03

DIN = 0x81

SEL=0x03

DIN = 0x00

SEL = 0x00

DIN = addr[15:8]

SEL = 0x01

DIN=addr[7:0]

Write

Read

Set ADDRH

Set ADDRL

As sert XE&

PROG

As sert NVSTR

Set ADDRL

Set DATA

As sert YE

Deassert YE

Set ADDRH

Set ADDRL

Address Val id to

Data Val id

No, increm ent YADDR

Yes

Deassert PROG

Deassert XE&

NVSTR

No, increm ent YADDR

Yes

20 us

SEL =
PWM2H,PWM1L,PWM1H

DIO =
PWM2L,PORT[A6:A0]

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