SE95 - Ultra High Accuracy Digital Temperature Sensor and Thermal Watchdoge
SE95D - Ultra high accuracy digital temperature sensor and thermal WatchdogE
SE95DP - Ultra high accuracy digital temperature sensor and thermal WatchdogE
SE98PW - SO-DIMM SMBus/I2C-bus temperature sensorGeneral descriptionThe SE98 isA JEDEC compliant local temperature sensor specifically designed for higher performance SO-DIMM applications. The temperature sensor is mounted on the SO-DIMM module and communicates with the processor via the I2C-bus/SMBus. Since the DRAM refresh rate is dependent on temperature, mounting the temperature sensor on the module allows the processor to adjust the refresh rate based on the actual temperature instead of the calculated worst-c
SE98PW/1 - SO-DIMM SMBus/I2C-bus temperature sensorGeneral descriptionThe SE98 isA JEDEC compliant local temperature sensor specifically designed for higher performance SO-DIMM applications. The temperature sensor is mounted on the SO-DIMM module and communicates with the processor via the I2C-bus/SMBus. Since the DRAM refresh rate is dependent on temperature, mounting the temperature sensor on the module allows the processor to adjust the refresh rate based on the actual temperature instead of the calculated worst-c
SE98TK - SO-DIMM SMBus/I2C-bus temperature sensorGeneral descriptionThe SE98 isA JEDEC compliant local temperature sensor specifically designed for higher performance SO-DIMM applications. The temperature sensor is mounted on the SO-DIMM module and communicates with the processor via the I2C-bus/SMBus. Since the DRAM refresh rate is dependent on temperature, mounting the temperature sensor on the module allows the processor to adjust the refresh rate based on the actual temperature instead of the calculated worst-c
SE98TK/1 - SO-DIMM SMBus/I2C-bus temperature sensorGeneral descriptionThe SE98 isA JEDEC compliant local temperature sensor specifically designed for higher performance SO-DIMM applications. The temperature sensor is mounted on the SO-DIMM module and communicates with the processor via the I2C-bus/SMBus. Since the DRAM refresh rate is dependent on temperature, mounting the temperature sensor on the module allows the processor to adjust the refresh rate based on the actual temperature instead of the calculated worst-c
SJA2020 - ARM7 microcontroller with CAN and LIN controllersThe SJA2020 consists of an ARM7TDMI-S processor with real-time emulation support, the AMBA Advanced High-performance Bus (AHB) for interface to the on-chip memory controllers,A DTL bus (a universal Philips interface) for interface to the interrupt controller and three VLSI Peripheral Buses (VPB -A compatible superset of ARMs AMBA advanced peripheral bus) for connection to the on-chip peripherals clustered in so-called subsystems. The SJA2020 configures the
SSTL16857 - 14-bit Sstl_2 Registered Driver With Differential Clock Inputs
SSTL16857DGG - 14-bit SSTL_2 registered driver with differential clock inputs
SSTL16877 - 14-bit Sstl_2 Registered Driver With Differential Clock Inputs
SSTL16877DGG - 14-bit SSTL_2 registered driver with differential clock inputs
SSTU32864 - 1.8V Configurable Registered Buffer For DDR2 Rdimm Applications The SSTU32864 isA 25-bit 1:1 or 14-bit 1:2 Configurable Registered Buffer Designed For 1.7V to 1.9V VDD Operation. All Clock and Data Inputs Are Compatible With The Jedec Standard to SSTL_18. The Control Inputs Are Lvcmos. All Outputs Are 1.8V CMOS Drivers That Have Been Optimized to Drive The DDR2 Dimm Load. The SSTU32864 Operates FromA Differential Clock (CK and CK). Data Are Registered at The Crossing of CK Going High, and CK Going Low
SSTU32864EC - 1.8V Configurable Registered Buffer For DDR2 Rdimm Applications The SSTU32864 isA 25-bit 1:1 or 14-bit 1:2 Configurable Registered Buffer Designed For 1.7V to 1.9V VDD Operation. All Clock and Data Inputs Are Compatible With The Jedec Standard to SSTL_18. The Control Inputs Are Lvcmos. All Outputs Are 1.8V CMOS Drivers That Have Been Optimized to Drive The DDR2 Dimm Load. The SSTU32864 Operates FromA Differential Clock (CK and CK). Data Are Registered at The Crossing of CK Going High, and CK Going Low
SSTU32864EC/G - 1.8V Configurable Registered Buffer For DDR2 Rdimm Applications The SSTU32864 isA 25-bit 1:1 or 14-bit 1:2 Configurable Registered Buffer Designed For 1.7V to 1.9V VDD Operation. All Clock and Data Inputs Are Compatible With The Jedec Standard to SSTL_18. The Control Inputs Are Lvcmos. All Outputs Are 1.8V CMOS Drivers That Have Been Optimized to Drive The DDR2 Dimm Load. The SSTU32864 Operates FromA Differential Clock (CK and CK). Data Are Registered at The Crossing of CK Going High, and CK Going Low
SSTU32865 - 1.8V 28-bit 1:2 Registered Buffer With Parity For Ddr2 Rdimm
SSTU32865EG - 1.8V 28-bit 1:2 registered buffer with parity for DDR2 RDIMM
SSTU32865ET - 1.8V 28-bit 1:2 registered buffer with parity for DDR2 RDIMM
SSTU32865ET/G - 1.8V 28-bit 1:2 Registered Buffer With Parity For DDR2 Rdimm Applicationsthe SSTU32865 isA 1.8V 28-bit 1:2 Register Specifically Designed For Use on Two Rank BY Four (2Rx4) and Similar High-density DDR2 Memory Modules. It is Similar in Function to The Jedec-standard 14-bit DDR2 Register, But Integrates The Functionality of The Normally Required Two Registers inA Single Package, Thereby Freeing up Board Real-estate and Facilitating Routing to Accommodate High-density Dimm Designs. The SSTU32865 Also Inte
SSTU32866 - 1.8V 25-bit 1:1 or 14-bit 1:2 Configurable Registered Buffer With Parity For DDR2 Rdimm Applications The SSTU32866 isA 1.8V Configurable Register Specifically Designed For Use on DDR2 Memory Modules RequiringA Parity Checking Function. It is Defined in Accordance With The Jedec JESD82-7 Standard For The SSTU32864 Registered Buffer, While Adding The Parity Checking Function inA Compatible Pinout. The Jedec Standard For SSTU32866 is Pending Publication. The Register is Configurable (using Configuration P
SSTU32866EC - 1.8V 25-bit 1:1 or 14-bit 1:2 Configurable Registered Buffer With Parity For DDR2 Rdimm Applications The SSTU32866 isA 1.8V Configurable Register Specifically Designed For Use on DDR2 Memory Modules RequiringA Parity Checking Function. It is Defined in Accordance With The Jedec JESD82-7 Standard For The SSTU32864 Registered Buffer, While Adding The Parity Checking Function inA Compatible Pinout. The Jedec Standard For SSTU32866 is Pending Publication. The Register is Configurable (using Configuration P
SSTU32866EC/G - 1.8V 25-bit 1:1 or 14-bit 1:2 Configurable Registered Buffer With Parity For DDR2 Rdimm Applications The SSTU32866 isA 1.8V Configurable Register Specifically Designed For Use on DDR2 Memory Modules RequiringA Parity Checking Function. It is Defined in Accordance With The Jedec JESD82-7 Standard For The SSTU32864 Registered Buffer, While Adding The Parity Checking Function inA Compatible Pinout. The Jedec Standard For SSTU32866 is Pending Publication. The Register is Configurable (using Configuration P
SSTUA32864 - 1.8V Configurable Registered Buffer For Ddr2-667 Rdimm Applications
SSTUA32864EC - 1.8V configurable registered buffer for DDR2-667 RDIMM applications
SSTUA32864EC/G - 1.8V configurable registered buffer for DDR2-667 RDIMM applicationsThe SSTUA32864 isA 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer designed for 1.7V to 2.0V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8V CMOS drivers that have been optimized to drive the DDR2 DIMM load. The SSTUA32864 operates fromA differential clock (CK and CK). Data are registered at the crossing of CK going HIGH, and CK
SSTUA32864EG - 1.8V configurable registered buffer for DDR2-667 RDIMM applications
SSTUA32866 - 1.8V 25-bit 1 : 1 Or 14-bit 1 : 2 Configurable Registered Buffer With Parity For Ddr2-667 Rdimm Applications
SSTUA32866EC - 1.8V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2-667 RDIMM applications
SSTUA32866EC-G - 1.8V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2-667 RDIMM applications
SSTUA32866EC/G-S - 1.8V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2-667 RDIMM applicationsThe SSTUA32866 isA 1.8V configurable register specifically designed for use on DDR2 memory modules requiringA parity checking function. It is defined in accordance with the JEDEC standard for the SSTUA32866 registered buffer. The register is configurable (using configuration pins C0 and C1) to two topologies: 25-bit 1 : 1 or 14-bit 1 : 2, and in the latter configuration can be designated as Regist
SSTUA32866EC/G-T - 1.8V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2-667 RDIMM applicationsThe SSTUA32866 isA 1.8V configurable register specifically designed for use on DDR2 memory modules requiringA parity checking function. It is defined in accordance with the JEDEC standard for the SSTUA32866 registered buffer. The register is configurable (using configuration pins C0 and C1) to two topologies: 25-bit 1 : 1 or 14-bit 1 : 2, and in the latter configuration can be designated as Regist
SSTUA32866EC-S - 1.8V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2-667 RDIMM applicationsThe SSTUA32866 isA 1.8V configurable register specifically designed for use on DDR2 memory modules requiringA parity checking function. It is defined in accordance with the JEDEC standard for the SSTUA32866 registered buffer. The register is configurable (using configuration pins C0 and C1) to two topologies: 25-bit 1 : 1 or 14-bit 1 : 2, and in the latter configuration can be designated as Regist
SSTUA32866EC-T - 1.8V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2-667 RDIMM applicationsThe SSTUA32866 isA 1.8V configurable register specifically designed for use on DDR2 memory modules requiringA parity checking function. It is defined in accordance with the JEDEC standard for the SSTUA32866 registered buffer. The register is configurable (using configuration pins C0 and C1) to two topologies: 25-bit 1 : 1 or 14-bit 1 : 2, and in the latter configuration can be designated as Regist
SSTUH32864 - 1.8V high output drive configurable registered buffer for DDR2 RDIMM applicationsThe SSTUH32864 isA 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer designed for 1.7V to 1.9V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8V CMOS drivers that have been optimized to drive the DDR2 DIMM load. The SSTUH32864 operates fromA differential clock (CK and CK). Data are registered at the crossing of CK goin
SSTUH32864EC - 1.8V high output drive configurable registered buffer for DDR2 RDIMM applicationsThe SSTUH32864 isA 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer designed for 1.7V to 1.9V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8V CMOS drivers that have been optimized to drive the DDR2 DIMM load. The SSTUH32864 operates fromA differential clock (CK and CK). Data are registered at the crossing of CK goin
SSTUH32864EC/G - 1.8V high output drive configurable registered buffer for DDR2 RDIMM applicationsThe SSTUH32864 isA 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer designed for 1.7V to 1.9V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8V CMOS drivers that have been optimized to drive the DDR2 DIMM load. The SSTUH32864 operates fromA differential clock (CK and CK). Data are registered at the crossing of CK goin
SSTUH32865 - 1.8V 28-bit high output drive 1:2 registered buffer with parity for DDR2 RDIMM applicationsThe SSTUH32865 isA 1.8V 28-bit high output drive 1:2 register specifically designed for use on two rank by four (2R x 4) and similar high-density Double Data Rate 2 (DDR2) memory modules. It is similar in function to the JEDEC-standard 14-bit DDR2 register, but integrates the functionality of the normally required two registers inA single package, thereby freeing up board real-estate and facilitating routing to ac
SSTUH32865ET - 1.8V 28-bit high output drive 1:2 registered buffer with parity for DDR2 RDIMM applicationsThe SSTUH32865 isA 1.8V 28-bit high output drive 1:2 register specifically designed for use on two rank by four (2R x 4) and similar high-density Double Data Rate 2 (DDR2) memory modules. It is similar in function to the JEDEC-standard 14-bit DDR2 register, but integrates the functionality of the normally required two registers inA single package, thereby freeing up board real-estate and facilitating routing to ac
SSTUH32865ET/G - 1.8V 28-bit high output drive 1:2 registered buffer with parity for DDR2 RDIMM applicationsThe SSTUH32865 isA 1.8V 28-bit high output drive 1:2 register specifically designed for use on two rank by four (2R x 4) and similar high-density Double Data Rate 2 (DDR2) memory modules. It is similar in function to the JEDEC-standard 14-bit DDR2 register, but integrates the functionality of the normally required two registers inA single package, thereby freeing up board real-estate and facilitating routing to ac
SSTUH32866 - 1.8V high output drive 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2 RDIMM applicationsThe SSTUH32866 isA 1.8V configurable register specifically designed for use on DDR2 memory modules requiringA parity checking function. It is defined in accordance with the JEDEC JESD82-7 standard for the SSTU32864 registered buffer, while adding the parity checking function inA compatible pinout. The JEDEC standard for SSTUH32866 is pending publication. The register is configurable
SSTUH32866EC - 1.8V high output drive 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2 RDIMM applicationsThe SSTUH32866 isA 1.8V configurable register specifically designed for use on DDR2 memory modules requiringA parity checking function. It is defined in accordance with the JEDEC JESD82-7 standard for the SSTU32864 registered buffer, while adding the parity checking function inA compatible pinout. The JEDEC standard for SSTUH32866 is pending publication. The register is configurable
SSTUH32866EC/G - 1.8V high output drive 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2 RDIMM applicationsThe SSTUH32866 isA 1.8V configurable register specifically designed for use on DDR2 memory modules requiringA parity checking function. It is defined in accordance with the JEDEC JESD82-7 standard for the SSTU32864 registered buffer, while adding the parity checking function inA compatible pinout. The JEDEC standard for SSTUH32866 is pending publication. The register is configurable
SSTV16857 - 14-bit Sstl_2 Registered Driver With Differential Clock Inputs
SSTV16857DGG - 14-bit SSTL_2 registered driver with differential clock inputs
SSTV16857DGV - 14-bit SSTL_2 registered driver with differential clock inputs
SSTV16857EV - 14-bit SSTL_2 registered driver with differential clock inputs
SSTV16859BS - 2.5V 13-bit to 26-bit SSTL_2 Registered Buffer For Stacked DDR DIMM; Package: SOT536-1 (LFBGA96), SOT646-1 (TSSOP64), SOT684-1 (HVQFN56)
SSTV16859DGG - 2.5V 13-bit to 26-bit SSTL_2 Registered Buffer For Stacked DDR DIMM; Package: SOT536-1 (LFBGA96), SOT646-1 (TSSOP64), SOT684-1 (HVQFN56)
SSTV16859EC - 2.5V 13-bit to 26-bit SSTL_2 Registered Buffer For Stacked DDR DIMM; Package: SOT536-1 (LFBGA96), SOT646-1 (TSSOP64), SOT684-1 (HVQFN56)
SSTVF16859 - 13-bit 1:2 SSTL_2 Registered Buffer For DDR The SSTVF16859 isA 13-bit to 26-bit SSTL_2 Registered Driver With Differential Clock Inputs, Designed to Operate Between 2.3V and 2.7V For PC1600 PC2700 Applications or Between 2.5V and 2.7V For PC3200 Applications. All Inputs Are Compatible With The Jedec Standard For SSTL_2 With Vref Normally at 0.5*VDD, Except The Lvcmos Reset (RESET) Input. All Outputs Are SSTL_2, Class ii Compatible Which CAN be Used For Standard Stub-Series Applications or Capacitive Lo
SSTVN16859 - 13-bit 1:2 Sstl_2 Registered Buffer For Ddr
SSTVN16859BS - 13-bit 1:2 SSTL_2 registered buffer for DDR
STM1/4/16 - Sdh/sonet Data and Clock Recovery Unit
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