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Электронный компонент: ICS8732AY-01

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8732AY-01
www.icst.com/products/hiperclocks.html
REV. C JUNE 23, 2003
1
Integrated
Circuit
Systems, Inc.
ICS8732-01
L
OW
V
OLTAGE
, L
OW
S
KEW
3.3V LVPECL C
LOCK
G
ENERATOR
G
ENERAL
D
ESCRIPTION
The ICS8732-01 is a low voltage, low skew,
3.3V LVPECL Clock Generator and a member of
the HiPerClockSTM family of High Performance
Clock Solutions from ICS. The ICS8732-01 has
two selectable clock inputs. The CLK0, nCLK0
pair can accept most standard differential input levels.
The single ended clock input accepts LVCMOS or LVTTL
input levels. The ICS8732-01 has a fully integrated PLL along
with frequency configurable outputs. An external feedback
input and outputs regenerate clocks with "zero delay".
The ICS8732-01 has multiple divide select pins for each bank
of outputs along with 3 independent feedback divide select
pins allowing the ICS8732-01 to function both as a frequency
multiplier and divider. The PLL_SEL input can be used
to bypass the PLL for test and system debug purposes.
In bypass mode, the input clock is routed around the PLL
and into the internal output dividers.
Features
10 differential 3.3V LVPECL outputs
Selectable differential CLK0, nCLK0 or
LVCMOS/LVTTL CLK1 inputs
CLK0, nCLK0 supports the following input types:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
CLK1 accepts the following input levels:
LVCMOS or LVTTL
Maximum output frequency: 350MHz
VCO range: 250MHz to 700MHz
External feedback for "zero delay" clock regeneration
with configurable frequencies
Cycle-to-cycle jitter: CLK0, nCLK0, 50ps (maximum)
CLK1, 80ps (maximum)
Output skew: 150ps (maximum)
Static phase offset: -150ps to 150ps
Industrial temperature information available upon request
HiPerClockSTM
,&6
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
V
CCO
QFB1
nQFB1
QFB0
nQFB0
V
EE
V
CC
FB_IN
nFB_IN
FBDIV_SEL0
FBDIV_SEL1
FBDIV_SEL2
V
EE
1
2
3
4
5
6
7
8
9
10
11
12
13
14 15 16 17 18 19 20 21 22 23 24 25 26
39
38
37
36
35
34
33
32
31
30
29
28
27
52 51 50 49 48 47 46 45 44 43 42 41 40
V
CCO
QA0
nQA0
QA1
nQA1
V
EE
PLL_SEL
V
CCO
QA2
nQA2
QA3
nQA3
V
EE
V
CCO
nQB3
QB3
nQB2
QB2
V
EE
MR
V
CCO
nQB1
QB1
nQB0
QB0
V
EE
V
CC
DIV_SELB0
DIV_SELB1
nc
V
CCA
CLK_SEL
CLK0
nCLK0
CLK1
V
EE
V
CC
DIV_SELA0
DIV_SELA1
52-Lead LQFP
10mm x 10mm x 1.4mm package body
Y package
Top View
ICS8732-01
REF_SEL
CLK0
nCLK0
CLK1
FB_IN
nFB_IN
PLL_SEL
DIV_SELA0
DIV_SELA1
DIV_SELB0
DIV_SELB1
FBDIV_SEL0
FBDIV_SEL1
FBDIV_SEL2
MR
QA0
nQA0
QA1
nQA1
QA2
nQA2
QA3
nQA3
0
1
PLL
0
1
QB0
nQB0
QB1
nQB1
QB2
nQB2
QB3
nQB3
QFB0
nQFB0
QFB1
nQFB1
2 4 6 8
2 4 8 12
4 6 8 10
8 12 16 20
8732AY-01
www.icst.com/products/hiperclocks.html
REV. C JUNE 23, 2003
2
Integrated
Circuit
Systems, Inc.
ICS8732-01
L
OW
V
OLTAGE
, L
OW
S
KEW
3.3V LVPECL C
LOCK
G
ENERATOR
T
ABLE
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8732AY-01
www.icst.com/products/hiperclocks.html
REV. C JUNE 23, 2003
3
Integrated
Circuit
Systems, Inc.
ICS8732-01
L
OW
V
OLTAGE
, L
OW
S
KEW
3.3V LVPECL C
LOCK
G
ENERATOR
T
ABLE
2. P
IN
C
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M
l
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c
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p
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m
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p
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I
1
5
K
T
ABLE
3A. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
FOR
QA0:QA3 O
UTPUTS
s
t
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p
n
I
s
t
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p
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M
L
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S
_
L
L
P
1
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L
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_
V
I
D
0
A
L
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_
V
I
D
3
A
Q
n
:
0
A
Q
n
,
3
A
Q
:
0
A
Q
1
X
X
X
w
o
L
0
1
0
0
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/
O
C
V
f
0
1
0
1
4
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V
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0
1
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0
6
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1
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K
L
C
_
F
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R
f
T
ABLE
3B. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
FOR
QB0:QB3 O
UTPUTS
s
t
u
p
n
I
s
t
u
p
t
u
O
R
M
L
E
S
_
L
L
P
1
B
L
E
S
_
V
I
D
0
B
L
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S
_
V
I
D
3
B
Q
n
:
0
B
Q
n
,
3
B
Q
:
0
B
Q
1
X
X
X
w
o
L
0
1
0
0
2
/
O
C
V
f
0
1
0
1
4
/
O
C
V
f
0
1
1
0
8
/
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C
V
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L
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L
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1
1
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1
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K
L
C
_
F
E
R
f
8732AY-01
www.icst.com/products/hiperclocks.html
REV. C JUNE 23, 2003
4
Integrated
Circuit
Systems, Inc.
ICS8732-01
L
OW
V
OLTAGE
, L
OW
S
KEW
3.3V LVPECL C
LOCK
G
ENERATOR
T
ABLE
4A. Q
X
O
UTPUT
F
REQUENCY
W
/FB_IN = QFB0
OR
QFB1
s
t
u
p
n
I
O
C
V
f
N
I
_
B
F
2
L
E
S
_
V
I
D
B
F
1
L
E
S
_
V
I
D
B
F
0
L
E
S
_
V
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D
B
F
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d
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M
r
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d
i
v
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D
t
u
p
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O
)
z
H
M
(
1
K
L
C
)
1
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T
O
N
(
m
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m
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n
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M
m
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M
B
F
Q
0
0
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4
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2
6
5
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1
)
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T
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4
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1
4
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2
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1
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7
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3
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T
ABLE
3C. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
FOR
QFB0, QFB1
s
t
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p
n
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s
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f
0
0
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1
6
/
K
L
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_
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0
0
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1
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8
/
K
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C
_
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f
0
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1
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/
K
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0
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f
8732AY-01
www.icst.com/products/hiperclocks.html
REV. C JUNE 23, 2003
5
Integrated
Circuit
Systems, Inc.
ICS8732-01
L
OW
V
OLTAGE
, L
OW
S
KEW
3.3V LVPECL C
LOCK
G
ENERATOR
T
ABLE
5A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, T
A
= 0C
TO
70C
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
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n
o
C
t
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T
m
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m
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M
l
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c
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p
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T
m
u
m
i
x
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M
s
t
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U
V
C
C
e
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y
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p
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C
5
3
1
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3
3
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3
5
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4
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3
V
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5
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3
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3
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3
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3
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3
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w
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5
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ABLE
5B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, T
A
= 0C
TO
70C
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x
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B
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V
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C
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=
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5
6
4
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3
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0
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1
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=
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w
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L
C
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L
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V
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D
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x
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L
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_
V
I
D
x
L
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S
_
V
I
D
B
F
V
C
C
,
V
5
6
4
.
3
=
V
N
I
V
0
=
5
-
A
L
E
S
_
L
L
P
V
C
C
,
V
5
6
4
.
3
=
V
N
I
V
0
=
0
5
1
-
A
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
4.6V
Inputs, V
I
-0.5V to V
CC
+ 0.5 V
Outputs, I
O
Continuous Current
50mA
Surge Current
100mA
Package Thermal Impedance,
JA
42.3C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
8732AY-01
www.icst.com/products/hiperclocks.html
REV. C JUNE 23, 2003
6
Integrated
Circuit
Systems, Inc.
ICS8732-01
L
OW
V
OLTAGE
, L
OW
S
KEW
3.3V LVPECL C
LOCK
G
ENERATOR
T
ABLE
5D. LVPECL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, T
A
= 0C
TO
70C
T
ABLE
7. AC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, T
A
= 0C
TO
70C
l
o
b
m
y
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r
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6. PLL I
NPUT
R
EFERENCE
C
HARACTERISTICS
,
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CC
= V
CCA
= V
CCO
= 3.3V5%, T
A
= 0C
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HARACTERISTICS
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-
8732AY-01
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REV. C JUNE 23, 2003
7
Integrated
Circuit
Systems, Inc.
ICS8732-01
L
OW
V
OLTAGE
, L
OW
S
KEW
3.3V LVPECL C
LOCK
G
ENERATOR
P
ARAMETER
M
EASUREMENT
I
NFORMATION
C
YCLE
-
TO
-C
YCLE
J
ITTER
S
TATIC
P
HASE
O
FFSET
O
UTPUT
R
ISE
/F
ALL
T
IME
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
V
SW I N G
tsk(o)
nQx
Qx
nQy
Qy
D
IFFERENTIAL
I
NPUT
L
EVEL
O
UTPUT
S
KEW
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
Qx
nQx
LVPECL
V
CMR
Cross Points
V
PP
V
ee
CLK0,
FB_IN
nCLK0,
nFB_IN
V
cc
nQA0:nQA3,
nQB0:nQB3,
nQFB0,
nQFB1
QA0:QA3,
QB0:QB3,
QFB0, QFB1
nCLK0
CLK0,
CLK1
nFB_IN
FB_IN
t()
V
OH
V
OL
V
OH
V
OL
V
ee
= -1.3V 0.165V
V
cc
, V
cca
, V
cco
= 2V
odc & t
P
ERIOD
Pulse Width
t
PERIOD
t
PW
t
PERIOD
odc =
nQA:nQA3,
nQFB0, nQFB1
QA:QA3,
QFB0, QFB1
t
jit(cc) =
t
cycle n
t
cycle n+1
1000 Cycles
t
cycle n
t
cycle n+1
8732AY-01
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REV. C JUNE 23, 2003
8
Integrated
Circuit
Systems, Inc.
ICS8732-01
L
OW
V
OLTAGE
, L
OW
S
KEW
3.3V LVPECL C
LOCK
G
ENERATOR
A
PPLICATION
I
NFORMATION
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminat-
ing resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
F
IGURE
2B. LVPECL O
UTPUT
T
ERMINATION
3.3V
F
OUT
F
IN
5
2 Z
o
Z
o
5
2
Z
o
3
2
Z
o
3
2
Z
o
= 50
Z
o
= 50
F
IGURE
2A. LVPECL O
UTPUT
T
ERMINATION
RTT =
1
(V
OH
+ V
OL
/ V
CC
2) 2
Z
o
Z
o
= 50
Z
o
= 50
50
50
RTT
V
CC
- 2V
F
IN
F
OUT
drive 50
transmission lines. Matched impedance techniques
should be used to maximize operating frequency and minimize
signal distortion.
Figures 2A and 2B show two different layouts
which are recommended only as guidelines. Other suitable clock
layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
T
ERMINATION
FOR
LVPECL O
UTPUTS
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
CC
/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
F
IGURE
1. S
INGLE
E
NDED
S
IGNAL
D
RIVING
D
IFFERENTIAL
I
NPUT
W
IRING
THE
D
IFFERENTIAL
I
NPUT
TO
A
CCEPT
S
INGLE
E
NDED
L
EVELS
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
CC
= 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
V_REF
R1
1K
C1
0.1u
R2
1K
Single Ended Clock Input
CLK
nCLK
VCC
8732AY-01
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REV. C JUNE 23, 2003
9
Integrated
Circuit
Systems, Inc.
ICS8732-01
L
OW
V
OLTAGE
, L
OW
S
KEW
3.3V LVPECL C
LOCK
G
ENERATOR
F
IGURE
4C. H
I
P
ER
C
LOCK
S CLK/
N
CLK I
NPUT
D
RIVEN
BY
3.3V LVPECL D
RIVER
F
IGURE
4B. H
I
P
ER
C
LOCK
S CLK/
N
CLK I
NPUT
D
RIVEN
BY
3.3V LVPECL D
RIVER
F
IGURE
4D. H
I
P
ER
C
LOCK
S CLK/
N
CLK I
NPUT
D
RIVEN
BY
3.3V LVDS D
RIVER
3.3V
R1
50
R3
50
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
3.3V
Input
R2
50
Zo = 50 Ohm
Input
HiPerClockS
CLK
nCLK
3.3V
R3
125
R2
84
Zo = 50 Ohm
3.3V
R4
125
LVPECL
R1
84
3.3V
D
IFFERENTIAL
C
LOCK
I
NPUT
I
NTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both V
SWING
and V
OH
must meet the
V
PP
and V
CMR
input requirements. Figures 4A to 4D show inter-
face examples for the HiPerClockS CLK/nCLK input driven by
the most common driver types. The input interfaces suggested
here are examples only. Please consult with the vendor of the
F
IGURE
4A. H
I
P
ER
C
LOCK
S CLK/
N
CLK I
NPUT
D
RIVEN
BY
ICS H
I
P
ER
C
LOCK
S LVHSTL D
RIVER
1.8V
R2
50
Input
LVHSTL Driver
ICS
HiPerClockS
R1
50
LVHSTL
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
Zo = 50 Ohm
R1
100
3.3V
LVDS_Driv er
Zo = 50 Ohm
Receiv er
CLK
nCLK
3.3V
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS8732-01 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V
CC
and V
CCA
should
be individually connected to the power supply plane through
vias, and bypass capacitors should be used for each pin. To
achieve optimum jitter performance, power supply isolation is
required.
Figure 3 illustrates how a 10
resistor along with a
10
F and a .01
F bypass capacitor should be connected to
each V
CCA
pin.
F
IGURE
3. P
OWER
S
UPPLY
F
ILTERING
10
V
CCA
10
F
.01
F
3.3V
.01
F
V
CC
P
OWER
S
UPPLY
F
ILTERING
T
ECHNIQUES
driver component to confirm the driver termination requirements.
For example in
Figure 4A, the input termination applies for ICS
HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
from another vendor, use their termination recommendation.
8732AY-01
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REV. C JUNE 23, 2003
10
Integrated
Circuit
Systems, Inc.
ICS8732-01
L
OW
V
OLTAGE
, L
OW
S
KEW
3.3V LVPECL C
LOCK
G
ENERATOR
P
OWER
C
ONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8732-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8732-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
CC
= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX
= V
CC_MAX
* I
EE_MAX
= 3.465V * 165mA = 572mW
Power (outputs)
MAX
= 30.2mW/Loaded Output pair
If all outputs are loaded, the total power is 10 * 30.2mW = 302mW
Total Power
_MAX
(3.465V, with all outputs switching) = 572mW + 302mW = 874mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS
TM
devices is 125C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 36.4C/W per Table 8 below.
Therefore, Tj for an ambient temperature of 70C with all outputs switching is:
70C + 0.874W * 36.4C/W = 102C. This is well below the limit of 125C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
q
JA
by Velocity (Linear Feet per Minute)
Table 8. Thermal Resistance
q
JA
for 52-pin LQFP, Forced Convection
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
58.0C/W
47.1C/W
42.0C/W
Multi-Layer PCB, JEDEC Standard Test Boards
42.3C/W
36.4C/W
34.0C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
8732AY-01
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REV. C JUNE 23, 2003
11
Integrated
Circuit
Systems, Inc.
ICS8732-01
L
OW
V
OLTAGE
, L
OW
S
KEW
3.3V LVPECL C
LOCK
G
ENERATOR
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in
Figure 5.
T
o calculate worst case power dissipation into the load, use the following equations which assume a 50
load, and a termination
voltage of V
CCO
- 2V.
For logic high, V
OUT
= V
OH_MAX
= V
CCO_MAX
1.0V
(V
CCO_MAX
- V
OH_MAX
) = 1.0V
For logic low, V
OUT
= V
OL_MAX
= V
CCO_MAX
1.7V
(V
CCO_MAX
- V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
(V
CCO_MAX
- 2V))/R
L
] * (V
CCO_MAX
- V
OH_MAX
) = [(2V - (V
CCO_MAX
- V
OH_MAX
))/R
L
] * (V
CCO_MAX
- V
OH_MAX
) =
[(2V - 1V)/50
] * 1V = 20.0mW
Pd_L = [(V
OL_MAX
(V
CCO_MAX
- 2V))/R
L
] * (V
CCO_MAX
- V
OL_MAX
) = [(2V - (V
CCO_MAX
- V
OL_MAX
))/R
L
] * (V
CCO_MAX
- V
OL_MAX
) =
[(2V - 1.7V)/50
] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
F
IGURE
5. LVPECL D
RIVER
C
IRCUIT
AND
T
ERMINATION
Q1
V
OUT
V
CCO
R L
50
V
CCO
- 2V
8732AY-01
www.icst.com/products/hiperclocks.html
REV. C JUNE 23, 2003
12
Integrated
Circuit
Systems, Inc.
ICS8732-01
L
OW
V
OLTAGE
, L
OW
S
KEW
3.3V LVPECL C
LOCK
G
ENERATOR
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS8732-01 is: 4916
T
ABLE
9.
JA
VS
. A
IR
F
LOW
T
ABLE
q
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
58.0C/W
47.1C/W
42.0C/W
Multi-Layer PCB, JEDEC Standard Test Boards
42.3C/W
36.4C/W
34.0C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
8732AY-01
www.icst.com/products/hiperclocks.html
REV. C JUNE 23, 2003
13
Integrated
Circuit
Systems, Inc.
ICS8732-01
L
OW
V
OLTAGE
, L
OW
S
KEW
3.3V LVPECL C
LOCK
G
ENERATOR
P
ACKAGE
O
UTLINE
- Y S
UFFIX
T
ABLE
10. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MS-026
N
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www.icst.com/products/hiperclocks.html
REV. C JUNE 23, 2003
14
Integrated
Circuit
Systems, Inc.
ICS8732-01
L
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V
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, L
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S
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3.3V LVPECL C
LOCK
G
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11. O
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I
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While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for
use in life support devices or critical medical instruments.
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www.icst.com/products/hiperclocks.html
REV. C JUNE 23, 2003
15
Integrated
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Systems, Inc.
ICS8732-01
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